14 lines
393 B
VHDL
14 lines
393 B
VHDL
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-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
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-- Module Version: 5.7
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-- Tue Apr 24 22:15:53 2018
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-- parameterized module component declaration
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component pll0
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port (CLKI: in std_logic; CLKOP: out std_logic;
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LOCK: out std_logic);
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end component;
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-- parameterized module component instance
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__ : pll0
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port map (CLKI=>__, CLKOP=>__, LOCK=>__);
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