2018-04-30 09:08:47 +02:00
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Starting process: Module
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Starting process:
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SCUBA, Version Diamond (64-bit) 3.10.0.111.2
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2020-05-10 20:47:47 +02:00
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Sun May 10 13:18:44 2020
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2018-04-30 09:08:47 +02:00
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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BEGIN SCUBA Module Synthesis
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2020-05-10 20:47:47 +02:00
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Issued command : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL
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2018-04-30 09:08:47 +02:00
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Circuit name : gram0
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Module type : RAM_DP_TRUE
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Module Version : 7.5
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Ports :
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Inputs : DataInA[8:0], DataInB[8:0], AddressA[12:0], AddressB[12:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
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Outputs : QA[8:0], QB[8:0]
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I/O buffer : not inserted
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2020-05-10 20:47:47 +02:00
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Memory file : /home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem
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2018-04-30 09:08:47 +02:00
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EDIF output : gram0.edn
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VHDL output : gram0.vhd
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VHDL template : gram0_tmpl.vhd
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VHDL testbench : tb_gram0_tmpl.vhd
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VHDL purpose : for synthesis and simulation
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Bus notation : big endian
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Report output : gram0.srp
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Estimated Resource Usage:
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LUT : 38
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EBR : 7
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Reg : 12
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END SCUBA Module Synthesis
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File: gram0.lpc created.
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End process: completed successfully.
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Total Warnings: 0
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Total Errors: 0
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