75 lines
1.9 KiB
VHDL
75 lines
1.9 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ram is
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generic(
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WIDTH : natural := 9;
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DEPTH : natural := 10
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);
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port(
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clk : in std_logic;
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rst : in std_logic; --
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a_addr_in : in std_logic_vector(DEPTH - 1 downto 0);
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a_data_in : in std_logic_vector(WIDTH - 1 downto 0);
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a_data_out : out std_logic_vector(WIDTH - 1 downto 0);
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a_we : in std_logic; --
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b_addr_in : in std_logic_vector(DEPTH - 1 downto 0);
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b_data_out : out std_logic_vector(WIDTH - 1 downto 0)
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);
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end entity ram;
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architecture RTL of ram is
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type memory_t is array (0 to 2**DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal memory : memory_t;
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begin
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mem_p : process(clk, rst) is
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begin
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if (rst = '1') then
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a_data_out <= (others => '0');
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b_data_out <= (others => '0');
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-- memory(0) <= "111100001";
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-- memory(1) <= "100101001";
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-- memory(2) <= "000000000";
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-- memory(3) <= "101010100";
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--
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-- memory(4) <= "111111111";
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-- memory(5) <= "000000000";
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-- memory(6) <= "000000000";
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-- memory(7) <= "000000000";
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----
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---- memory(0) <= "111111111";
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---- memory(1) <= "111111111";
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---- memory(2) <= "111111111";
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---- memory(3) <= "111111111";
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---- memory(4) <= "111111111";
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---- memory(5) <= "111111111";
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---- memory(6) <= "111111111";
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---- memory(7) <= "111111111";
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--
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-- memory(0) <= "101010101";
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-- memory(1) <= "101010100";
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-- memory(2) <= "101010101";
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-- memory(3) <= "101010100";
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--
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-- memory(4) <= "101010101";
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-- memory(5) <= "101010100";
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-- memory(6) <= "101010101";
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-- memory(7) <= "101010100";
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elsif (rising_edge(clk)) then
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a_data_out <= memory(to_integer(unsigned(a_addr_in)));
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b_data_out <= memory(to_integer(unsigned(b_addr_in)));
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if (a_we = '1') then
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memory(to_integer(unsigned(a_addr_in))) <= a_data_in;
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end if;
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end if;
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end process mem_p;
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end architecture RTL;
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