45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
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Starting process: Module
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Starting process:
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SCUBA, Version Diamond (64-bit) 3.10.0.111.2
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Tue Apr 24 22:15:53 2018
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
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BEGIN SCUBA Module Synthesis
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Issued command : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock
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Circuit name : pll0
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Module type : pll
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Module Version : 5.7
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Ports :
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Inputs : CLKI
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Outputs : CLKOP, LOCK
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I/O buffer : not inserted
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EDIF output : pll0.edn
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VHDL output : pll0.vhd
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VHDL template : pll0_tmpl.vhd
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VHDL purpose : for synthesis and simulation
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Bus notation : big endian
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Report output : pll0.srp
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Estimated Resource Usage:
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END SCUBA Module Synthesis
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File: pll0.lpc created.
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End process: completed successfully.
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Total Warnings: 0
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Total Errors: 0
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