46 lines
1003 B
VHDL
46 lines
1003 B
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.all;
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entity gram0 is
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port(
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DataInA : in std_logic_vector(8 downto 0);
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DataInB : in std_logic_vector(8 downto 0);
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AddressA : in std_logic_vector(12 downto 0);
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AddressB : in std_logic_vector(12 downto 0);
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ClockA : in std_logic;
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ClockB : in std_logic;
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ClockEnA : in std_logic;
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ClockEnB : in std_logic;
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WrA : in std_logic;
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WrB : in std_logic;
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ResetA : in std_logic;
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ResetB : in std_logic;
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QA : out std_logic_vector(8 downto 0);
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QB : out std_logic_vector(8 downto 0));
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end gram0;
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architecture RTL of gram0 is
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begin
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ram_inst : entity generics.ram
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generic map(
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WIDTH => 9,
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DEPTH => 13
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)
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port map(
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clk => ClockA,
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rst => ResetA,
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a_addr_in => AddressA,
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a_data_in => DataInA,
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a_data_out => QA,
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a_we => WrA,
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b_addr_in => AddressB,
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b_data_out => QB
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);
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end architecture RTL;
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