50 lines
1.8 KiB
Plaintext
50 lines
1.8 KiB
Plaintext
Starting process: Module
|
|
|
|
Starting process:
|
|
|
|
SCUBA, Version Diamond (64-bit) 3.10.0.111.2
|
|
Sun May 10 13:18:44 2020
|
|
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
|
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
|
|
|
BEGIN SCUBA Module Synthesis
|
|
|
|
Issued command : /usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n gram0 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdp -device LCMXO2-1200HC -aaddr_width 13 -widtha 9 -baddr_width 13 -widthb 9 -anum_words 7000 -bnum_words 7000 -outdataA REGISTERED -outdataB REGISTERED -cascade -1 -resetmode SYNC -sync_reset -memfile /home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem -memformat bin -writemodeA NORMAL -writemodeB NORMAL
|
|
Circuit name : gram0
|
|
Module type : RAM_DP_TRUE
|
|
Module Version : 7.5
|
|
Ports :
|
|
Inputs : DataInA[8:0], DataInB[8:0], AddressA[12:0], AddressB[12:0], ClockA, ClockB, ClockEnA, ClockEnB, WrA, WrB, ResetA, ResetB
|
|
Outputs : QA[8:0], QB[8:0]
|
|
I/O buffer : not inserted
|
|
Memory file : /home/markus/projects/cross-discipline/lw35-upgrade/display/tools/splash.mem
|
|
EDIF output : gram0.edn
|
|
VHDL output : gram0.vhd
|
|
VHDL template : gram0_tmpl.vhd
|
|
VHDL testbench : tb_gram0_tmpl.vhd
|
|
VHDL purpose : for synthesis and simulation
|
|
Bus notation : big endian
|
|
Report output : gram0.srp
|
|
Estimated Resource Usage:
|
|
LUT : 38
|
|
EBR : 7
|
|
Reg : 12
|
|
|
|
END SCUBA Module Synthesis
|
|
|
|
File: gram0.lpc created.
|
|
|
|
|
|
End process: completed successfully.
|
|
|
|
|
|
Total Warnings: 0
|
|
|
|
Total Errors: 0
|
|
|
|
|