25 lines
441 B
VHDL
25 lines
441 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pll0 is
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port(
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CLKI : in std_logic;
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CLKOP : out std_logic;
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LOCK : out std_logic);
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end entity pll0;
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architecture RTL of pll0 is
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begin
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LOCK <= '1';
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clock_driver : process
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constant period : time := (1 sec / 96000000);
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begin
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CLKOP <= '0';
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wait for period / 2;
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CLKOP <= '1';
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wait for period / 2;
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end process clock_driver;
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end architecture RTL;
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