30 lines
1.3 KiB
XML
30 lines
1.3 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<BaliProject version="3.2" title="lmg6202" device="LCMXO2-1200HC-5SG32C" default_implementation="impl1">
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<Options/>
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<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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<Options def_top="design.top" top="design.top"/>
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<Source name="../ip/gram0/gram0.ipx" type="IPX_Module" type_short="IPX">
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<Options/>
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</Source>
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<Source name="../design/lmg6202.vhd" type="VHDL" type_short="VHDL">
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<Options lib="design"/>
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</Source>
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<Source name="../design/top.vhd" type="VHDL" type_short="VHDL">
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<Options lib="design" top_module="design.top"/>
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</Source>
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<Source name="../ip/gram0/gram0.vhd" type="VHDL" type_short="VHDL">
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<Options lib="ip"/>
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</Source>
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<Source name="../design/spi_if.vhd" type="VHDL" type_short="VHDL">
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<Options lib="design"/>
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</Source>
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<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
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<Options/>
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</Source>
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<Source name="lmg6202.lpf" type="Logic Preference" type_short="LPF">
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<Options/>
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</Source>
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</Implementation>
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<Strategy name="Strategy1" file="lmg62021.sty"/>
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</BaliProject>
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