34 lines
589 B
VHDL
34 lines
589 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity synchronizer is
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generic(
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INIT : std_logic := '0'
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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din : in std_logic;
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dout : out std_logic
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);
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end entity synchronizer;
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architecture RTL of synchronizer is
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signal tmp : std_logic_vector(1 downto 0);
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begin
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sync_p : process(clk, rst) is
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begin
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if (rst = '1') then
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tmp <= (others => INIT);
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dout <= INIT;
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elsif (rising_edge(clk)) then
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tmp <= tmp(0) & din;
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dout <= tmp(1);
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end if;
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end process sync_p;
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end architecture RTL;
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