301 lines
9.7 KiB
Clojure
301 lines
9.7 KiB
Clojure
(edif pll0
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(edifVersion 2 0 0)
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(edifLevel 0)
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(keywordMap (keywordLevel 0))
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(status
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(written
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(timestamp 2018 4 24 22 15 53)
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(program "SCUBA" (version "Diamond (64-bit) 3.10.0.111.2"))))
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(comment "/usr/local/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll0 -lang vhdl -synth synplify -arch xo2c00 -type pll -fin 12 -fclkop 96 -fclkop_tol 0.0 -trimp 0 -phasep 0 -trimp_r -phase_cntl STATIC -fb_mode 1 -lock ")
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(library ORCLIB
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(edifLevel 0)
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(technology
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(numberDefinition))
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(cell VLO
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port Z
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(direction OUTPUT)))))
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(cell EHXPLLJ
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port CLKI
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(direction INPUT))
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(port CLKFB
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(direction INPUT))
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(port PHASESEL1
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(direction INPUT))
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(port PHASESEL0
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(direction INPUT))
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(port PHASEDIR
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(direction INPUT))
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(port PHASESTEP
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(direction INPUT))
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(port LOADREG
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(direction INPUT))
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(port STDBY
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(direction INPUT))
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(port PLLWAKESYNC
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(direction INPUT))
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(port RST
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(direction INPUT))
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(port RESETM
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(direction INPUT))
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(port RESETC
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(direction INPUT))
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(port RESETD
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(direction INPUT))
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(port ENCLKOP
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(direction INPUT))
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(port ENCLKOS
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(direction INPUT))
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(port ENCLKOS2
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(direction INPUT))
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(port ENCLKOS3
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(direction INPUT))
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(port PLLCLK
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(direction INPUT))
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(port PLLRST
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(direction INPUT))
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(port PLLSTB
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(direction INPUT))
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(port PLLWE
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(direction INPUT))
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(port PLLADDR4
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(direction INPUT))
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(port PLLADDR3
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(direction INPUT))
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(port PLLADDR2
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(direction INPUT))
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(port PLLADDR1
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(direction INPUT))
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(port PLLADDR0
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(direction INPUT))
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(port PLLDATI7
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(direction INPUT))
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(port PLLDATI6
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(direction INPUT))
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(port PLLDATI5
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(direction INPUT))
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(port PLLDATI4
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(direction INPUT))
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(port PLLDATI3
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(direction INPUT))
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(port PLLDATI2
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(direction INPUT))
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(port PLLDATI1
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(direction INPUT))
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(port PLLDATI0
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(direction INPUT))
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(port CLKOP
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(direction OUTPUT))
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(port CLKOS
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(direction OUTPUT))
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(port CLKOS2
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(direction OUTPUT))
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(port CLKOS3
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(direction OUTPUT))
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(port LOCK
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(direction OUTPUT))
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(port INTLOCK
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(direction OUTPUT))
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(port REFCLK
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(direction OUTPUT))
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(port CLKINTFB
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(direction OUTPUT))
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(port DPHSRC
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(direction OUTPUT))
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(port PLLACK
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(direction OUTPUT))
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(port PLLDATO7
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(direction OUTPUT))
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(port PLLDATO6
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(direction OUTPUT))
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(port PLLDATO5
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(direction OUTPUT))
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(port PLLDATO4
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(direction OUTPUT))
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(port PLLDATO3
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(direction OUTPUT))
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(port PLLDATO2
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(direction OUTPUT))
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(port PLLDATO1
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(direction OUTPUT))
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(port PLLDATO0
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(direction OUTPUT)))))
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(cell pll0
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(cellType GENERIC)
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(view view1
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(viewType NETLIST)
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(interface
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(port CLKI
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(direction INPUT))
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(port CLKOP
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(direction OUTPUT))
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(port LOCK
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(direction OUTPUT)))
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(property NGD_DRC_MASK (integer 1))
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(contents
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(instance scuba_vlo_inst
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(viewRef view1
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(cellRef VLO)))
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(instance PLLInst_0
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(viewRef view1
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(cellRef EHXPLLJ))
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(property DDRST_ENA
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(string "DISABLED"))
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(property DCRST_ENA
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(string "DISABLED"))
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(property MRST_ENA
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(string "DISABLED"))
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(property PLLRST_ENA
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(string "DISABLED"))
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(property INTFB_WAKE
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(string "DISABLED"))
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(property STDBY_ENABLE
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(string "DISABLED"))
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(property DPHASE_SOURCE
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(string "DISABLED"))
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(property PLL_USE_WB
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(string "DISABLED"))
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(property CLKOS3_FPHASE
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(string "0"))
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(property CLKOS3_CPHASE
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(string "0"))
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(property CLKOS2_FPHASE
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(string "0"))
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(property CLKOS2_CPHASE
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(string "0"))
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(property CLKOS_FPHASE
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(string "0"))
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(property CLKOS_CPHASE
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(string "0"))
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(property CLKOP_FPHASE
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(string "0"))
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(property CLKOP_CPHASE
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(string "4"))
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(property PLL_LOCK_MODE
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(string "0"))
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(property CLKOS_TRIM_DELAY
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(string "0"))
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(property CLKOS_TRIM_POL
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(string "FALLING"))
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(property CLKOP_TRIM_DELAY
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(string "0"))
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(property CLKOP_TRIM_POL
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(string "RISING"))
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(property FRACN_DIV
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(string "0"))
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(property FRACN_ENABLE
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(string "DISABLED"))
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(property OUTDIVIDER_MUXD2
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(string "DIVD"))
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(property PREDIVIDER_MUXD1
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(string "0"))
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(property VCO_BYPASS_D0
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(string "DISABLED"))
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(property CLKOS3_ENABLE
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(string "DISABLED"))
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(property OUTDIVIDER_MUXC2
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(string "DIVC"))
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(property PREDIVIDER_MUXC1
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(string "0"))
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(property VCO_BYPASS_C0
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(string "DISABLED"))
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(property CLKOS2_ENABLE
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(string "DISABLED"))
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(property OUTDIVIDER_MUXB2
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(string "DIVB"))
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(property PREDIVIDER_MUXB1
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(string "0"))
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(property VCO_BYPASS_B0
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(string "DISABLED"))
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(property CLKOS_ENABLE
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(string "DISABLED"))
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(property FREQUENCY_PIN_CLKOP
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(string "96.000000"))
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(property OUTDIVIDER_MUXA2
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(string "DIVA"))
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(property PREDIVIDER_MUXA1
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(string "0"))
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(property VCO_BYPASS_A0
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(string "DISABLED"))
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(property CLKOP_ENABLE
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(string "ENABLED"))
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(property FREQUENCY_PIN_CLKI
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(string "12.000000"))
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(property ICP_CURRENT
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(string "7"))
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(property LPF_RESISTOR
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(string "8"))
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(property CLKOS3_DIV
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(string "1"))
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(property CLKOS2_DIV
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(string "1"))
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(property CLKOS_DIV
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(string "1"))
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(property CLKOP_DIV
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(string "5"))
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(property CLKFB_DIV
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(string "8"))
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(property CLKI_DIV
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(string "1"))
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(property FEEDBK_PATH
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(string "CLKOP")))
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(net scuba_vlo
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(joined
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(portRef Z (instanceRef scuba_vlo_inst))
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(portRef PLLADDR4 (instanceRef PLLInst_0))
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(portRef PLLADDR3 (instanceRef PLLInst_0))
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(portRef PLLADDR2 (instanceRef PLLInst_0))
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(portRef PLLADDR1 (instanceRef PLLInst_0))
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(portRef PLLADDR0 (instanceRef PLLInst_0))
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(portRef PLLDATI7 (instanceRef PLLInst_0))
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(portRef PLLDATI6 (instanceRef PLLInst_0))
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(portRef PLLDATI5 (instanceRef PLLInst_0))
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(portRef PLLDATI4 (instanceRef PLLInst_0))
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(portRef PLLDATI3 (instanceRef PLLInst_0))
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(portRef PLLDATI2 (instanceRef PLLInst_0))
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(portRef PLLDATI1 (instanceRef PLLInst_0))
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(portRef PLLDATI0 (instanceRef PLLInst_0))
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(portRef PLLWE (instanceRef PLLInst_0))
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(portRef PLLSTB (instanceRef PLLInst_0))
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(portRef PLLRST (instanceRef PLLInst_0))
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(portRef PLLCLK (instanceRef PLLInst_0))
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(portRef ENCLKOS3 (instanceRef PLLInst_0))
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(portRef ENCLKOS2 (instanceRef PLLInst_0))
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(portRef ENCLKOS (instanceRef PLLInst_0))
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(portRef ENCLKOP (instanceRef PLLInst_0))
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(portRef RESETD (instanceRef PLLInst_0))
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(portRef RESETC (instanceRef PLLInst_0))
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(portRef RESETM (instanceRef PLLInst_0))
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(portRef RST (instanceRef PLLInst_0))
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(portRef PLLWAKESYNC (instanceRef PLLInst_0))
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(portRef STDBY (instanceRef PLLInst_0))
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(portRef LOADREG (instanceRef PLLInst_0))
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(portRef PHASESTEP (instanceRef PLLInst_0))
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(portRef PHASEDIR (instanceRef PLLInst_0))
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(portRef PHASESEL1 (instanceRef PLLInst_0))
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(portRef PHASESEL0 (instanceRef PLLInst_0))))
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(net LOCK
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(joined
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(portRef LOCK)
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(portRef LOCK (instanceRef PLLInst_0))))
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(net CLKOP
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(joined
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(portRef CLKOP)
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(portRef CLKFB (instanceRef PLLInst_0))
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(portRef CLKOP (instanceRef PLLInst_0))))
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(net CLKI
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(joined
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(portRef CLKI)
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(portRef CLKI (instanceRef PLLInst_0))))))))
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(design pll0
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(cellRef pll0
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(libraryRef ORCLIB)))
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)
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