121 lines
2.2 KiB
VHDL
121 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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entity bench_top is
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end entity bench_top;
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architecture RTL of bench_top is
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signal clk : std_logic;
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signal rst_hw : std_logic;
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signal lcd_data : std_logic_vector(3 downto 0);
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signal lcd_clp : std_logic;
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signal lcd_load : std_logic;
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signal lcd_frp : std_logic;
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signal lcd_frmb : std_logic;
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signal spi_cs_n : std_logic;
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signal spi_sck : std_logic;
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signal spi_mosi : std_logic;
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signal spi_miso : std_logic;
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begin
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top_inst : entity design.top
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port map(
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spi_cs_n => spi_cs_n,
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spi_sck => spi_sck,
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spi_mosi => spi_mosi,
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spi_miso => spi_miso,
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clk_hw => clk,
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rst_hw => rst_hw,
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lcd_data => lcd_data,
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lcd_clp => lcd_clp,
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lcd_load => lcd_load,
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lcd_frp => lcd_frp,
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lcd_frmb => lcd_frmb
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);
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clock_driver : process
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constant period : time := (1 sec / 24000000);
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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begin
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rst_hw <= '0';
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wait for 100 ns;
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rst_hw <= '1';
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wait;
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end process test;
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spitest : process is
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constant CPOL : std_logic := '0';
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constant DEL : time := 400 ns;
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procedure send_byte(data : std_logic_vector(7 downto 0)) is
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begin
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for i in 7 downto 0 loop
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spi_sck <= CPOL;
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wait for DEL;
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spi_mosi <= data(i);
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spi_sck <= not CPOL;
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wait for DEL;
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end loop;
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end procedure send_byte;
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begin
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spi_cs_n <= '1';
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spi_sck <= '0';
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spi_mosi <= CPOL;
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wait until rst_hw = '1';
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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spi_cs_n <= '0';
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wait for 400 ns;
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send_byte(x"00");
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send_byte(x"00");
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send_byte(x"00");
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send_byte(x"AB");
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send_byte(x"CD");
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send_byte(x"55");
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send_byte(x"AA");
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send_byte(x"81");
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send_byte(x"2A");
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send_byte(x"AB");
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send_byte(x"BC");
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send_byte(x"CF");
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send_byte(x"AB");
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send_byte(x"CD");
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send_byte(x"55");
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send_byte(x"AA");
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send_byte(x"81");
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send_byte(x"2A");
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send_byte(x"AB");
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send_byte(x"BC");
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send_byte(x"CF");
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spi_cs_n <= '1';
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wait;
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end process spitest;
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end architecture RTL;
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