lw35-upgrade/display/fpga/ip/gram0/gram0_tmpl.vhd
2018-04-30 09:08:47 +02:00

24 lines
1.0 KiB
VHDL

-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.0.111.2
-- Module Version: 7.5
-- Sun Apr 22 17:34:06 2018
-- parameterized module component declaration
component gram0
port (DataInA: in std_logic_vector(8 downto 0);
DataInB: in std_logic_vector(8 downto 0);
AddressA: in std_logic_vector(12 downto 0);
AddressB: in std_logic_vector(12 downto 0);
ClockA: in std_logic; ClockB: in std_logic;
ClockEnA: in std_logic; ClockEnB: in std_logic;
WrA: in std_logic; WrB: in std_logic; ResetA: in std_logic;
ResetB: in std_logic; QA: out std_logic_vector(8 downto 0);
QB: out std_logic_vector(8 downto 0));
end component;
-- parameterized module component instance
__ : gram0
port map (DataInA(8 downto 0)=>__, DataInB(8 downto 0)=>__, AddressA(12 downto 0)=>__,
AddressB(12 downto 0)=>__, ClockA=>__, ClockB=>__, ClockEnA=>__,
ClockEnB=>__, WrA=>__, WrB=>__, ResetA=>__, ResetB=>__, QA(8 downto 0)=>__,
QB(8 downto 0)=>__);