87 lines
1.8 KiB
Plaintext
87 lines
1.8 KiB
Plaintext
EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 4
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Title ""
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Date "2020-10-03"
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Rev "01"
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Comp "Macrocell"
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Comment1 "#followtheling"
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Comment2 ""
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Comment3 ""
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Comment4 "Schematic overview"
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$EndDescr
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$Sheet
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S 650 650 1400 1100
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U 5F7CBB94
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F0 "power" 50
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F1 "power.sch" 50
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$EndSheet
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Wire Wire Line
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3650 800 3850 800
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Wire Wire Line
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3650 900 3850 900
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Wire Wire Line
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3650 1000 3850 1000
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Wire Wire Line
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3650 1100 3850 1100
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Wire Wire Line
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3650 1250 3850 1250
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Wire Wire Line
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3650 1350 3850 1350
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Wire Wire Line
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3650 1450 3850 1450
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Wire Wire Line
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3650 1550 3850 1550
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Wire Wire Line
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3650 1700 3850 1700
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Wire Wire Line
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3650 1800 3850 1800
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Wire Wire Line
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3650 1900 3850 1900
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$Sheet
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S 2250 650 1400 1600
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U 5F7D680C
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F0 "cpu" 50
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F1 "cpu.sch" 50
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F2 "DMX_RO" I R 3650 800 50
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F3 "DMX_RE" O R 3650 900 50
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F4 "DMX_DI" O R 3650 1000 50
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F5 "DMX_DE" O R 3650 1100 50
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F6 "WS0_TX" O R 3650 1250 50
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F7 "WS1_TX" O R 3650 1450 50
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F8 "WS0_RX" I R 3650 1350 50
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F9 "CONTROL_UART_IN" I R 3650 1800 50
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F10 "CONTROL_UART_OUT" O R 3650 1700 50
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F11 "WS1_RX" I R 3650 1550 50
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F12 "CONTROL_UART_RST" I R 3650 1900 50
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F13 "AUDIO_L" I R 3650 2050 50
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F14 "AUDIO_R" I R 3650 2150 50
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$EndSheet
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$Sheet
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S 3850 650 1250 1600
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U 5F8467A7
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F0 "io" 50
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F1 "io.sch" 50
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F2 "DMX_RO" O L 3850 800 50
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F3 "DMX_RE" I L 3850 900 50
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F4 "DMX_DI" I L 3850 1000 50
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F5 "DMX_DE" I L 3850 1100 50
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F6 "WS0_TX" I L 3850 1250 50
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F7 "WS1_RX" O L 3850 1550 50
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F8 "WS1_TX" I L 3850 1450 50
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F9 "WS0_RX" O L 3850 1350 50
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F10 "USB_UART_IN" O L 3850 1800 50
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F11 "USB_UART_OUT" I L 3850 1700 50
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F12 "USB_UART_DTR" O L 3850 1900 50
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F13 "AUDIO_L" O L 3850 2050 50
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F14 "AUDIO_R" O L 3850 2150 50
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$EndSheet
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Wire Wire Line
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3650 2050 3850 2050
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Wire Wire Line
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3850 2150 3650 2150
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$EndSCHEMATC
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