doc: Add errata, change design, extend some paragraphs
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@ -13,6 +13,7 @@
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\acro{fpga} [FPGA] {field-programmable gate array}
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\acro{fpga} [FPGA] {field-programmable gate array}
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\acro{io} [I/O] {input / output}
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\acro{io} [I/O] {input / output}
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\acro{jtag} [JTAG] {Joint Test Action Group}
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\acro{jtag} [JTAG] {Joint Test Action Group}
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\acro{pll} [PLL] {phase locked loop}
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\acro{led} [LED] {light emitting diode}
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\acro{led} [LED] {light emitting diode}
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\acro{ldo} [LDO] {low-dropout regulator}
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\acro{ldo} [LDO] {low-dropout regulator}
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\acro{rx} [RX] {receive}
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\acro{rx} [RX] {receive}
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@ -30,6 +30,7 @@ pdflang=en,
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\usepackage{multirow}
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\usepackage{multirow}
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\usepackage{graphicx}
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\usepackage{graphicx}
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\usepackage{xcolor}
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\usepackage{xcolor}
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\usepackage{adjustbox}
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\usepackage{pdfpages}
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\usepackage{pdfpages}
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\usepackage{pdflscape}
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\usepackage{pdflscape}
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\usepackage[american]{babel}
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\usepackage[american]{babel}
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@ -44,7 +45,12 @@ bibencoding=utf8
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\addbibresource{lit.bib}
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\addbibresource{lit.bib}
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\DeclareLanguageMapping{american}{american-apa}
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\DeclareLanguageMapping{american}{american-apa}
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\newcommand\Warning{%
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\newcommand\hwmodSym{%
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\makebox[1.4em][c]{%
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\makebox[0pt][c]{\raisebox{.1em}{\small!}}%
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\makebox[0pt][c]{\color{blue}\Large$\bigtriangleup$}}}%
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\newcommand\WarningSym{%
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\makebox[1.4em][c]{%
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\makebox[1.4em][c]{%
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\makebox[0pt][c]{\raisebox{.1em}{\small!}}%
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\makebox[0pt][c]{\raisebox{.1em}{\small!}}%
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\makebox[0pt][c]{\color{red}\Large$\bigtriangleup$}}}%
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\makebox[0pt][c]{\color{red}\Large$\bigtriangleup$}}}%
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@ -63,7 +69,26 @@ bibencoding=utf8
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\setlength{\parindent}{0cm}
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\setlength{\parindent}{0cm}
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\setlength{\parskip}{1em}
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\setlength{\parskip}{1em}
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\newcommand{\hwmod}[1]{\paragraph{\Warning Hardware Modification \Warning} #1}
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\newcommand{\hwmod}[1]{
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\begin{center}
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\adjustbox{minipage=\textwidth,cfbox=blue}{
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\begin{center}
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\hwmodSym \textbf{Hardware Modification}\hwmodSym
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\end{center}
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#1
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}
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\end{center}
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}
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\newcommand{\Warning}[1]{
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\begin{center}
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\adjustbox{minipage=\textwidth,cfbox=red}{
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\begin{center}
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\WarningSym \textbf{Warning}\WarningSym
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\end{center}
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#1
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}
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\end{center}
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}
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\begin{document}
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\begin{document}
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@ -79,7 +104,7 @@ The Tiny-XO2 is a small, versatile and cost-effective development platform for t
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In addition to the \ac{fpga}, it provides a \ac{usb} to \ac{uart} converter and a crystal to include the basic set of components for any \ac{fpga} design.
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In addition to the \ac{fpga}, it provides a \ac{usb} to \ac{uart} converter and a crystal to include the basic set of components for any \ac{fpga} design.
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This manual applies to hardware revision 01.
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This manual applies to hardware revision 01. The latest version can be found online at \\ \url{https://l.notsyncing.net/tinyxo2}
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\chapter{Hardware}
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\chapter{Hardware}
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This chapter explains all available hardware functions.
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This chapter explains all available hardware functions.
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@ -119,9 +144,9 @@ The board can be powered either via \ac{usb} or using the \texttt{VB} pin on pin
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The \texttt{3V} pins on the pin headers can be used to supply the on-board generated 3.3 V to supporting circuitry. The maximum current to be drawn from these pins is 500 mA\footnote{The maximum current of the AP1117 voltage regulator is 800 mA\parencite[page 4]{tlv1117}. Watch the temperature of \texttt{U1} when drawing high amounts of current.}.
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The \texttt{3V} pins on the pin headers can be used to supply the on-board generated 3.3 V to supporting circuitry. The maximum current to be drawn from these pins is 500 mA\footnote{The maximum current of the AP1117 voltage regulator is 800 mA\parencite[page 4]{tlv1117}. Watch the temperature of \texttt{U1} when drawing high amounts of current.}.
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All \ac{io} pins on header \texttt{J3} use the voltage on pin \texttt{VX} as bank voltage. It may range from 1.2 V to 3.3 V \parencite[page 8]{ioguide}. By populating \texttt{R9} with a zero Ohm resistor, the bank can be connected to the on-board 3.3 V supply. In this case, \texttt{VX} becomes a normal \texttt{3V} pin. See chapter \ref{ioheaders} for more details.
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All \ac{io} pins on header \texttt{J3} use the voltage on pin \texttt{VX} as bank voltage. It may range from 1.2 V to 3.3 V \parencite[page 8]{ioguide}. By populating \texttt{R9} with a zero Ohm resistor, the bank can be connected to the on-board 3.3 V supply. In this case, \texttt{VX} becomes a normal \texttt{3V} pin.
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\hwmod{If a 2.5 V supply voltage is required for all \ac{io} pins, the main voltage regulator \texttt{U1} can be replaced with a 1117-2.5 2.5 V voltage regulator. The \ac{fpga} will continue to function normally in this case. When doing this, all \texttt{3V} pins carry 2.5 V. \texttt{VX} may be supplied with up to 3.3 V. \textbf{The CH340G \ac{usb}-to-serial converter will stop working in this configuration}, so it needs to be removed from the board.}
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\hwmod{If a 2.5 V supply voltage is required for all \ac{io} pins, the main voltage regulator \texttt{U1} can be replaced with a 1117-2.5 2.5 V voltage regulator. The \ac{fpga} will continue to function normally in this case. When doing this, all \texttt{3V} pins carry 2.5 V. \texttt{VX} may be supplied with up to 3.3 V. \textbf{The CH340G \ac{usb}-to-serial converter will stop working in this configuration} and needs to be removed from the board.}
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\section{\acs{fpga}}
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\section{\acs{fpga}}
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\label{fpga}
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\label{fpga}
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@ -175,16 +200,20 @@ Additionally, the \ac{rx} and \ac{tx} lines have an \ac{led} connected in parall
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\section{Crystal Oscillator}
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\section{Crystal Oscillator}
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\label{crystal}
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\label{crystal}
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The board features a 12 MHz crystal oscillator. It supplies the clock to the \ac{usb}-to-\ac{uart} converter and is also connected to pin \texttt{28} of the \ac{fpga}. If the 12 MHz clock signal is not needed on the \ac{fpga}, resistor \texttt{R2} can be removed to free pin \texttt{28} as a general purpose \ac{io} pin.
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The board features a 12 MHz crystal oscillator. It supplies the clock to the \ac{usb}-to-\ac{uart} converter and is also connected to pin \texttt{28} of the \ac{fpga}. If the 12 MHz clock signal is not needed on the \ac{fpga}, resistor \texttt{R2} can be removed to free pin \texttt{28} as a general purpose \ac{io} pin. A higher frequency for the design can be generated using the \ac{pll} inside the \ac{fpga}.
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\hwmod{If another base frequency is required, the crystal oscillator on the back (\texttt{U4}) can be exchanged with another value. \textbf{The CH340G \ac{usb}-to-\ac{uart} coverter will stop working in this configuration} and needs to be removed from the board.}
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\section{\acs{io} Headers}
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\section{\acs{io} Headers}
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\label{ioheaders}
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\label{ioheaders}
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The \ac{io} headers break out all available \ac{io} pins of the \ac{fpga}. The pin number is marked next to each pin on the board.
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The \ac{io} headers break out all available \ac{io} pins of the \ac{fpga}. The pin number is marked next to each pin on the board.
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Header \texttt{J3} has no special functions and uses \texttt{VX} as bank voltage. This voltage can be tied to the 3.3 V supply of the board by installing a zero ohm resistor for component \texttt{R9}.
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Header \texttt{J3} has no special functions and uses \texttt{VX} as bank voltage. This voltage can be tied to the 3.3 V supply of the board either by installing a zero ohm resistor for component \texttt{R9} or by installing a jumper between the \texttt{VX} and \texttt{3V} pin. Refer to chapter \ref{power} for more information on \ac{io} voltages.
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Header \texttt{J4} has special functions assigned to most of its pins. Refer to Table \ref{tab:iofunctions} for a comprehensive list. In order to use these pins as general purpose \ac{io} pins, refer to the respective chapter. All \ac{io} pins on header \texttt{J4} use 3.3 V as bank voltage.
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Header \texttt{J4} has special functions assigned to most of its pins. Refer to Table \ref{tab:iofunctions} for a comprehensive list. In order to use these pins as general purpose \ac{io} pins, refer to the respective chapter. All \ac{io} pins on header \texttt{J4} use 3.3 V as bank voltage.
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Note that the \ac{jtag} pins are connected in parallel to the \ac{jtag} header \texttt{J2} and the corresponding pins on \texttt{J4}.
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\begin{table}[h]
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\begin{table}[h]
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\caption{\acs{io} pin special functions}
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\caption{\acs{io} pin special functions}
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\label{tab:iofunctions}
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\label{tab:iofunctions}
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@ -276,9 +305,11 @@ Pin \texttt{26} is not available as user \ac{io} in this configuration. Care nee
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\subsection{\acs{uart} Bootloader}
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\subsection{\acs{uart} Bootloader}
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\label{progopt:bootloader}
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\label{progopt:bootloader}
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\textit{NYI. TODO.}
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The MachXO2 devices can be programmed from the active design. This allows the user to entirely disable all external programming interfaces which makes all \ac{io} pins available to the user logic.
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{\color{red}WARNING: Setting these parameters will \textbf{permanently} disable the \ac{jtag} port. This might render the device unusable. Only apply this if you really know what you are doing.}
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At the current point in time, this functionality has not been implemented.
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\Warning{Setting these parameters will \textbf{permanently} disable the \ac{jtag} port. This might render the device unusable. Only apply this if you really know what you are doing.}
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\begin{table}[h]
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\begin{table}[h]
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\caption{Preferences for bootloader mode}
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\caption{Preferences for bootloader mode}
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@ -293,6 +324,11 @@ Pin \texttt{26} is not available as user \ac{io} in this configuration. Care nee
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All \ac{io} pins are available as user \acp{io}.
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All \ac{io} pins are available as user \acp{io}.
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\chapter{Errata}
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\section*{Hardware Revision 01}
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\paragraph{TLV1117-33 decoupling.}
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The board is missing the 10+ $\mu F$ capacitor on the output of the 1117-3.3 voltage regulator (\texttt{U1}). This might cause instability with certain devices. This problem can be easily solved by installing a 10 $\mu F$ 0805 capacitor right next to \texttt{C7}. Revision 02 addresses this issue.
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\chapter{Appendix}
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\chapter{Appendix}
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\section{Version History}
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\section{Version History}
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@ -302,7 +338,7 @@ All \ac{io} pins are available as user \acp{io}.
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\centering
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\centering
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\begin{tabular}{ll} \toprule
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\begin{tabular}{ll} \toprule
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\textbf{Version} & \textbf{Comment} \\ \midrule
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\textbf{Version} & \textbf{Comment} \\ \midrule
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2017-11-25 & DTR usage, 2.5 V mod \\
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2017-11-27 & DTR usage, 2.5 V mod, errata, editorial changes \\
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2017-11-20 & Fix \ac{jtag} TDI pin number \\
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2017-11-20 & Fix \ac{jtag} TDI pin number \\
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2017-11-16 & Editorial changes \\
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2017-11-16 & Editorial changes \\
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2017-11-10 & Initial draft \\ \bottomrule
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2017-11-10 & Initial draft \\ \bottomrule
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