Add documentation draft
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doc/.gitignore
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doc/.gitignore
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*.aux
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*~
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*.bbl
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*.bcf
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*.blg
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*.log
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*.run.xml
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*.synctex.gz
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*.toc
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*.pdf
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*.svg
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!res/*
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doc/acro.tex
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% Sort using emacs:
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% http://rtime.felk.cvut.cz/~sojka/blog/sorting-latex-acronyms-in-emacs/
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%I press C-up to go to \begin{ and then left. This moves me at the end of the
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% elisp expression.
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% Press C-x C-e (eval-last-sexp) and the list is sorted!
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\chapter*{List of Abbreviations}
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\addcontentsline{toc}{chapter}{List of Abbreviations}
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% Sort acronyms: (let ((sort-fold-case t)) (sort-regexp-fields nil "^[[:space:]]*\\\\acro\{\\([^}]*\\)\}.*$" "\\1" (point-min) (point-max)))
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% \acro{} {}
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\begin{acronym}[TDMA]
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%
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\acro{fpga} [FPGA] {field-programmable gate array}
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\acro{uart} [UART] {universal asynchronous receiver / transmitter}
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\acro{jtag} [JTAG] {Joint Test Action Group}
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\acro{usb} [USB] {universal serial bus}
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\acro{led} [LED] {light emitting diode}
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\acro{io} [I/O] {input / output}
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\acro{ldo} [LDO] {low-dropout regulator}
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\acro{rx} [RX] {receive}
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\acro{tx} [TX] {transmit}
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\acro{} [] {}
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\acro{} [] {}
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\end{acronym}
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#!/bin/bash
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for file in ./*.dia; do
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p=${file%.dia}
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p=${p##*/}
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outfile="$p.svg"
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dia --export=$outfile $file
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done
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for file in ./*.svg; do
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p=${file%.svg}
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p=${p##*/}
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outfile="$p.pdf"
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inkscape -D -z --file="$file" --export-pdf="$outfile" #--export-latex
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done
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% This file was created with JabRef 2.10.
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% Encoding: UTF8
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@Manual{tlv1117,
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Title = {TLV1117 Adjustable and Fixed Low-Dropout Voltage Regulator},
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Author = {Texas~Instruments},
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Month = {12},
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Year = {2014},
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Owner = {markus},
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Timestamp = {2017.11.10},
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Url = {http://www.ti.com/lit/ds/symlink/tlv1117.pdf}
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}
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@Manual{progcable,
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Title = {Programming Cables User Guide},
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Author = {Lattice~Semiconductor},
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Edition = {Version 25.0},
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Month = {11},
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Year = {2016},
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Owner = {markus},
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Timestamp = {2017.11.10},
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Url = {http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/MQ/ProgrammingCableUsersGuide.pdf?document_id=143}
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}
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@Manual{machxo2conf,
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Title = {MachXO2 Programming and Configuration Usage Guide},
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Author = {Lattice~Semiconductor},
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Month = {7},
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Year = {2017},
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Owner = {markus},
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Timestamp = {2017.11.10},
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Url = {http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/MO/MachXO2ProgrammingandConfigurationUsageGuide.pdf?document_id=39085}
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}
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@Manual{machxo2family,
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Title = {MachXO2TM Family Data Sheet},
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Author = {Lattice~Semiconductor},
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Edition = {Version 3.3},
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Month = {3},
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Year = {2017},
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Owner = {markus},
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Timestamp = {2017.11.10},
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Url = {http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf?document_id=38834}
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}
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doc/tiny-xo2-documentation.tex
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% Notes:
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% http://www.ti.com/lit/ds/symlink/tlv1117.pdf
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% http://www.latticesemi.com/~/media/LatticeSemi/Documents/UserManuals/MQ/ProgrammingCableUsersGuide.pdf?document_id=143
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% http://www.latticesemi.com/~/media/LatticeSemi/Documents/ApplicationNotes/MO/MachXO2ProgrammingandConfigurationUsageGuide.pdf?document_id=39085
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% http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf?document_id=38834
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\documentclass[openany,oneside]{scrbook}
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\usepackage[printonlyused, withpage]{acronym}
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\usepackage{booktabs}
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\usepackage{graphicx}
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\usepackage{color}
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\usepackage{pdfpages}
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\usepackage{pdflscape}
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\usepackage[american]{babel}
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\usepackage[babel,german=quotes]{csquotes}
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\usepackage[
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backend=biber,
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style=numeric,
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natbib,
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bibencoding=utf8
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%apabackref=true,
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]{biblatex}
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\addbibresource{lit.bib}
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\DeclareLanguageMapping{american}{american-apa}
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\usepackage{draftwatermark}
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\SetWatermarkScale{5}
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\SetWatermarkLightness{0.94}
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\title{Tiny-XO2 Development Kit}
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\author{Markus Koch $\langle$markus@notsyncing.net$\rangle$}
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\publishers{\centering\includegraphics[width=.55\textwidth]{img/coverpage.png}}
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\setlength{\parindent}{0cm}
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\setlength{\parskip}{1em}
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\begin{document}
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\maketitle
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\include{acro}
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\tableofcontents
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\chapter{Introduction}
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The Tiny-XO2 is a small, versatile and cost-effective development platform for the Lattice MachXO2 \acp{fpga}.
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In addition to the \ac{fpga}, it provides a \ac{usb} to \ac{uart} converter and a crystal to include the basic set of components for any \ac{fpga} design.
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\chapter{Hardware}
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In this chapter, all available hardware functions are explained.
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\section{Overview}
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Figure \ref{fig:overview} and Table \ref{tab:overview} show an overview of all the functions of the board.
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\begin{figure}[h]
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\centering
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\includegraphics[width=\textwidth]{img/overview.pdf}
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\caption{Board overview}
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\label{fig:overview}
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\end{figure}
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\begin{table}[h]
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\caption{Board function list}
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\label{tab:overview}
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\centering
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\begin{tabular}{ll} \toprule
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1 & \acs{jtag} programming header \\
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2 & Lattice LCMXO2-1200HC \acs{fpga} \\
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3 & Power LED (Orange) \\
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4 & \acs{uart} \acs{tx} (Board $\rightarrow$ PC) \acs{led} (Red) \\
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5 & \acs{uart} \acs{rx} (PC $\rightarrow$ Board) \acs{led} (Green) \\
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6 & \acs{usb} socket for \acs{uart} and power \\
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\midrule
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7 & \acs{io} headers \\
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8 & 12 MHz crystal oscillator for \acs{fpga} and \acs{usb}-to-\acs{uart} converter \\
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9 & CH340G \acs{usb} to \acs{uart} converter \\
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10 & 5 V to 3.3 V \ac{ldo} \\ \bottomrule
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\end{tabular}
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\end{table}
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\section{Power Supply}
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\label{power}
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The board can be powered either via \ac{usb} or using the \texttt{VB} pin on pin header \texttt{J3}. The input voltage can range from 5 V to 15 V \parencite[page 4]{tlv1117}. A diode between the \ac{usb} jack and the \texttt{VB} pin prevents backfeeding of current into the \ac{usb} connection.
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The \texttt{3V} pins on the pin headers can be used to supply the on-board generated 3.3 V to supporting circuitry. The maximum current to be drawn from these pins is 500 mA \footnote{The maximum current of the AP1117 voltage regulator is 800 mA\parencite[page 4]{tlv1117}. Watch the temperature of the IC when drawing high amounts of current.}.
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All \ac{io} pins on header \texttt{J3} use the voltage on pin \texttt{VX} as bank voltage. By populating \texttt{R9} with a zero Ohm resistor, the bank can be connected to the on-board 3.3 V supply. In this case, \texttt{VX} becomes a normal \texttt{3V} pin. See chapter \ref{ioheaders} for more details.
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\section{\acs{fpga}}
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\label{fpga}
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The \ac{fpga} present on the board is a Lattice LCMXO2-1200HC-\emph{4}SG32C or LCMXO2-1200HC-\emph{6}SG32C.
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\begin{table}[h]
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\caption{Main features of the \ac{fpga} \parencite[page 3]{machxo2family}}
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\label{tab:fpgafeatures}
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\centering
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\begin{tabular}{ll} \toprule
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\textbf{Property} & \textbf{Value} \\
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\ac{io} & 21* \\
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LUTs & 1280 \\
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Distributed RAM & 10 kbits \\
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EBR SRAM & 64 kbits \\
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User flash & 64 kbits \\
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Hard IPs & 2x i2c, 1x SPI, 1x Timer / Counter, 1x PLL \\ \bottomrule
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\end{tabular}
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\\ \textit{* Not all \acp{io} may be usable. Refer to chapter \ref{ioheaders}.}
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\end{table}
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Depending on the version of the board, either speedgrade 4 or 6 are installed. Check the marking on the chip to determine which version applies.
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\section{\acs{uart} and \acsp{led}}
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\label{uart}
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The board features a CH340G \ac{usb}-to-\ac{uart} converter. Its \ac{tx} line is connected to pin \texttt{21}, the \ac{rx} line is connected to pin \texttt{20}. Pin \texttt{23} is connected to the DTR signal from the chip, which is pulled low as soon as the terminal is opened on the PC.
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Additionally, the \ac{rx} and \ac{tx} lines have an \ac{led} connected in parallel. Should a specific \ac{led} or \ac{uart} function be not wanted, refer to table \ref{tab:uartresistors} to see how to disable individual features.
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\begin{table}[h]
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\caption{Resistors to disable \ac{uart} functions}
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\label{tab:uartresistors}
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\centering
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\begin{tabular}{cll} \toprule
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\textbf{Resistor} & \textbf{Description} \\ \midrule
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R6 & \ac{uart} \ac{tx} \\
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R7 & \ac{uart} \ac{rx} \\
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R8 & \ac{uart} DTR \\
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\midrule
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R4 & \ac{tx} \ac{led} \\
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R5 & \ac{rx} \ac{led} \\ \bottomrule
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\end{tabular}
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\end{table}
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\section{Crystal Oscillator}
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\label{crystal}
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The board features a 12 MHz crystal oscillator. This is used to supply the clock to the \ac{usb}-to-\ac{uart} converter and is also connected to pin \texttt{28} of the \ac{fpga}. If the 12 MHz clock signal is not needed on the \ac{fpga}, resistor \texttt{R2} can be removed to free pin \texttt{28} as a general purpose \ac{io} pin.
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\section{\acs{io} Headers}
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\label{ioheaders}
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The \ac{io} headers break out all available \ac{io} pins of the \ac{fpga}.
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Header \texttt{J3} has no special functions and uses \texttt{VX} as bank voltage. This voltage can be tied to the 3.3 V supply of the board by installing a zero ohm resistor for component \texttt{R9}.
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Header \texttt{J4} has special functions assigned to most of its pins. Refer to Table \ref{tab:iofunctions} for a comprehensive list. In order to use these pins as general purpose \ac{io} pins, refer to the respective chapter. All \ac{io} pins on header \texttt{J4} use 3.3 V as bank voltage.
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\begin{table}[h]
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\caption{\acs{io} pin special functions}
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\label{tab:iofunctions}
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\centering
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\begin{tabular}{cll} \toprule
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\textbf{Pins} & \textbf{Description} & \textbf{Note} \\ \midrule
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\texttt{26} & \acs{jtag} multiplex & See chapter \ref{progopt:multiplex} \\
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\texttt{29}, \texttt{30}, \texttt{31}, \texttt{01} & \acs{jtag} & See chapter \ref{progopt:always} \\
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\texttt{20}, \texttt{21}, \texttt{23} & \acs{uart} & See chapter \ref{uart} \\
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\texttt{28} & 12 MHz clock & See chapter \ref{crystal} \\ \bottomrule
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\end{tabular}
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\end{table}
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\chapter{Software Configuration}
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\section{Comparison}
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\begin{table}[h]
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\caption{Comparison of configuration methods}
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\label{tab:confcompare}
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\centering
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\begin{tabular}{lcl} \toprule
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\textbf{Type} & \textbf{Available \acs{io}} & \textbf{Note} \\ \midrule
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Always-active \acs{jtag} & \texttt{18} & Advanced debugging possible\\
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Multiplexed \acs{jtag} & \texttt{21} & Special consideration for 4 pins \\
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Bootloader / None & \texttt{22} & Chip can not be recovered on error\\ \bottomrule
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\end{tabular}
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\end{table}
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\section{Programming Options}
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\label{progopt}
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\subsection{Always-active \acs{jtag}}
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\label{progopt:always}
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This is the simplest of all configuration methods. It is supported by any Lattice programmer, including the FTDI FTxxxx based ones.
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To use this method, no special configuration needs to be applied in the Lattice Diamond software. The programming preferences in the \textit{global preferences} in the spreadsheet view should look like this \parencite{machxo2conf}:
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\begin{table}[h]
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\caption{Preferences for always-active \ac{jtag} mode}
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\label{tab:prefmux}
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\centering
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\begin{tabular}{lcl} \toprule
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\textbf{Name} & \textbf{Value} \\ \midrule
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JTAG\_PORT & ENABLE\\
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MUX\_CONFIGURATION\_PORTS & DISABLE \\ \bottomrule
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\end{tabular}
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\end{table}
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The following connections need to be made between the programmer and the \ac{jtag} header \texttt{J2}: TDO (\texttt{TO}), TDI (\texttt{TI}), TCK (\texttt{TC}), TMS (\texttt{TM}).
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Pins 29, 30, 31 and 01 are not available as user \ac{io} in this configuration. All other pins are available as normal user \ac{io}.
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\subsection{Multiplexed \acs{jtag}}
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\label{progopt:multiplex}
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This configuration allows to use the \ac{jtag} pins as normal user \ac{io} as long as some parameters are kept in mind.
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In this mode, the function of pins \texttt{29}, \texttt{30}, \texttt{31} and \texttt{01} is switched using pin \texttt{26} (\texttt{EN}). This pin needs to be pulled low to enable \ac{jtag} mode. This can either be done manually before each programming operation or by using the \texttt{PROGRAMN} pin available on Lattice programmers. To make the automatic switchover work, the following settings need to be applied in the Diamond software \parencite{progcable}:
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\begin{figure}[h]
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\centering
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\includegraphics[width=.5\textwidth]{img/jtagmuxset.png}
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\caption{\ac{jtag} settings for automatic pin multiplexing}
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\label{fig:jtagmuxset}
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\end{figure}
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To enable this mode, the following settings need to be configured in the \textit{global preferences} in the spreadsheet view in Lattice Diamond:
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\begin{table}[h]
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\caption{Preferences for multiplexed \ac{jtag} mode}
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\label{tab:prefmux}
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\centering
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\begin{tabular}{lcl} \toprule
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\textbf{Name} & \textbf{Value} \\ \midrule
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JTAG\_PORT & DISABLE \\
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MUX\_CONFIGURATION\_PORTS & ENABLE \\ \bottomrule
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\end{tabular}
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\end{table}
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When programming the \ac{fpga} in circuit, the user needs to ensure that all \ac{jtag} lines are high-Z when programming actions are active (when \texttt{26} (\texttt{EN}) is low). Also, the \ac{jtag} bit patterns should not affect any components attached to the \ac{jtag} pins during a programming operation.
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The following connections need to be made between the programmer and the \ac{jtag} header \texttt{J2}: TDO (\texttt{TO}), TDI (\texttt{TI}), TCK (\texttt{TC}), TMS (\texttt{TM}), PROGRAMN (\texttt{EN}).
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Pin \texttt{26} is not available as user \ac{io} in this configuration. Care needs to be taken when selecting which components to connect to pins \texttt{29}, \texttt{30}, \texttt{31} and \texttt{01}. All other pins are available as normal user \ac{io}.
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\subsection{\acs{uart} Bootloader}
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\label{progopt:bootloader}
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\textit{NYI. TODO.}
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{\color{red}WARNING: Setting these parameters will \textbf{permanently} disable the \ac{jtag} port. This might render the device unusable. Only apply this if you really know what you are doing.}
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\begin{table}[h]
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\caption{Preferences for bootloader mode}
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\label{tab:prefmux}
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\centering
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\begin{tabular}{lcl} \toprule
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\textbf{Name} & \textbf{Value} \\ \midrule
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JTAG\_PORT & DISABLE \\
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MUX\_CONFIGURATION\_PORTS & DISABLE \\ \bottomrule
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\end{tabular}
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\end{table}
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All \ac{io} pins are available as user \ac{io}.
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\chapter{Appendix}
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\section{Version History}
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\begin{table}[h]
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\caption{Version history}
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\label{tab:versionhistory}
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\centering
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\begin{tabular}{ll} \toprule
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\textbf{Version} & \textbf{Comment} \\ \midrule
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2017-11-10 & Initial draft\\ \bottomrule
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\end{tabular}
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\end{table}
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\section{Bibliography}
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\printbibliography[heading=none]
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\section{Schematic}
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See next page.
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\begin{landscape}
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\includepdf[angle=90,pages={1-}]{res/schematic.pdf}
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\end{landscape}
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\end{document}
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