trashernet-soc/fpga/hdl/design/servant_gpio_vhdl.vhd

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2024-06-12 20:03:04 +02:00
-- -------------------------------------------------------------------------- --
-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
-- -------------------------------------------------------------------------- --
-- TODO
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library generics;
use generics.wishbone_pkg.all;
entity servant_gpio_vhdl is
port(
clk : in std_logic; -- CPU and bus clock
clr : in std_logic; -- Synchronous clear (CPU reset)
wb_o : out wishbone_slave_out; -- Instruction Wishbone bus (out)
wb_i : in wishbone_slave_in; -- Instruction Wishbone bus (in)
output : out std_logic -- System Timer Interrupt
);
end entity servant_gpio_vhdl;
architecture rtl of servant_gpio_vhdl is
component servant_gpio
port(
i_wb_clk : in std_logic;
i_wb_dat : in std_logic;
i_wb_we : in std_logic;
i_wb_cyc : in std_logic;
o_wb_rdt : out std_logic;
o_gpio : out std_logic
);
end component servant_gpio;
begin
servant_gpio_inst : component servant_gpio
port map(
i_wb_clk => clk,
i_wb_dat => wb_i.dat(0),
i_wb_we => wb_i.we,
i_wb_cyc => wb_i.cyc and wb_i.stb,
o_wb_rdt => wb_o.dat(0),
o_gpio => output
);
wb_o.ack <= '1';
wb_o.rty <= '0';
wb_o.err <= '0';
wb_o.stall <= '0';
wb_o.dat(31 downto 1) <= (others => '0');
end architecture rtl;