trashernet-soc/fpga/hdl/generics/ice40_components.vhd

library ieee;
use ieee.std_logic_1164.all;

package ice40_components is
	component SB_PLL40_PAD
		generic(
			FEEDBACK_PATH : string;
			DIVR          : std_logic_vector(3 downto 0);
			DIVF          : std_logic_vector(6 downto 0);
			DIVQ          : std_logic_vector(2 downto 0);
			FILTER_RANGE  : std_logic_vector(2 downto 0)
		);
		port(
			RESETB       : in  std_logic;
			BYPASS       : in  std_logic;
			PACKAGEPIN   : in  std_logic;
			PLLOUTCORE   : out std_logic;
			PLLOUTGLOBAL : out std_logic
		);
	end component SB_PLL40_PAD;

	component SB_PLL40_2_PAD
		generic(
			FEEDBACK_PATH : string;
			DIVR          : std_logic_vector(3 downto 0);
			DIVF          : std_logic_vector(6 downto 0);
			DIVQ          : std_logic_vector(2 downto 0);
			FILTER_RANGE  : std_logic_vector(2 downto 0)
		);
		port(
			RESETB        : in  std_logic;
			BYPASS        : in  std_logic;
			PACKAGEPIN    : in  std_logic;
			PLLOUTCOREA   : out std_logic;
			PLLOUTCOREB   : out std_logic;
			PLLOUTGLOBALA : out std_logic;
			PLLOUTGLOBALB : out std_logic
		);
	end component SB_PLL40_2_PAD;

	component SB_PLL40_2_CORE
		generic(
			FEEDBACK_PATH : string;
			DIVR          : std_logic_vector(3 downto 0);
			DIVF          : std_logic_vector(6 downto 0);
			DIVQ          : std_logic_vector(2 downto 0);
			FILTER_RANGE  : std_logic_vector(2 downto 0)
		);
		port(
			RESETB       : in  std_logic;
			BYPASS       : in  std_logic;
			REFERENCECLK : in  std_logic;
			PLLOUTCOREA  : out std_logic;
			PLLOUTCOREB  : out std_logic
		);
	end component SB_PLL40_2_CORE;

	component SB_PLL40_CORE
		generic(
			FEEDBACK_PATH : string := "SIMPLE";
			--			DELAY_ADJUSTMENT_MODE_FEEDBACK : string                       := "FIXED";
			--			DELAY_ADJUSTMENT_MODE_RELATIVE : string                       := "FIXED";
			--			PLLOUT_SELECT                  : string                       := "GENCLK";
			--			SHIFTREG_DIV_MODE              : std_logic;
			--			FDA_FEEDBACK                   : std_logic_vector(3 downto 0) := "1111";
			--			FDA_RELATIVE                   : std_logic_vector(3 downto 0) := "1111";
			DIVR          : std_logic_vector(3 downto 0);
			DIVF          : std_logic_vector(6 downto 0);
			DIVQ          : std_logic_vector(2 downto 0);
			FILTER_RANGE  : std_logic_vector(2 downto 0)
			--			ENABLE_ICEGATE                 : std_logic                    := '0';
			--			TEST_MODE                      : std_logic                    := '0'
		);
		port(
			REFERENCECLK : in  std_logic;
			PLLOUTCORE   : out std_logic;
			PLLOUTGLOBAL : out std_logic;
			--			EXTFEEDBACK     : in  std_logic;
			--			DYNAMICDELAY    : in  std_logic_vector(7 downto 0);
			LOCK         : out std_logic;
			BYPASS       : in  std_logic;
			RESETB       : in  std_logic
			--			LATCHINPUTVALUE : in  std_logic;
			--			SDO             : out std_logic;
			--			SDI             : in  std_logic;
			--			SCLK            : in  std_logic
		);
	end component SB_PLL40_CORE;

	component SB_HFOSC
		generic(
			CLKHF_DIV : string
		);
		port(
			CLKHFPU : in  std_logic;
			CLKHFEN : in  std_logic;
			CLKHF   : out std_logic
		);
	end component SB_HFOSC;

	COMPONENT SB_IO IS
		GENERIC(
			PIN_TYPE    : std_logic_vector(5 downto 0) := "000000";
			IO_STANDARD : string                       := "SB_LVDS_INPUT"
		);
		PORT(
			PACKAGE_PIN       : in  std_logic;
			LATCH_INPUT_VALUE : in  std_logic;
			CLOCK_ENABLE      : in  std_logic;
			INPUT_CLK         : in  std_logic;
			OUTPUT_CLK        : in  std_logic;
			OUTPUT_ENABLE     : in  std_logic;
			D_OUT_0           : in  std_logic;
			D_OUT_1           : in  std_logic;
			D_IN_0            : out std_logic;
			D_IN_1            : out std_logic
		);
	END COMPONENT SB_IO;

	component SB_GB
		port(
			USER_SIGNAL_TO_GLOBAL_BUFFER : in  std_logic;
			GLOBAL_BUFFER_OUTPUT         : out std_logic);
	end component;
end package ice40_components;