trashernet-soc/fpga/hdl/design/trashernet_phy_wb.vhd

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-- -------------------------------------------------------------------------- --
-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
-- -------------------------------------------------------------------------- --
-- TODO
-- -------------------------------------------------------------------------- --
-- Author : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library trashernet;
use trashernet.trashernet_pkg.all;
library generics;
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use generics.all;
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use generics.wishbone_pkg.all;
entity trashernet_phy_wb is
generic(
F_CLK : in integer; -- Clock frequency in Hz
F_CLK_PHY : in integer
);
port(
-- Global
clk : in std_logic; -- Global clock
phy_clk : in std_logic; -- PHY clock
rst : in std_logic; -- Asynchronous reset
-- Wishbone IF
wb_o : out wishbone_slave_out; -- Wishbone bus (out)
wb_i : in wishbone_slave_in; -- Wishbone bus (in)
-- Ethernet physical signals
rx_p : in std_logic;
tx_p : out std_logic;
tx_n : out std_logic
);
end entity trashernet_phy_wb;
architecture RTL of trashernet_phy_wb is
-- PHY application interface
signal phy_out : phy_out_t; -- PHY application IF (out)
signal phy_in : phy_in_t; -- PHY application IF (in)
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signal wb_adr : unsigned(2 downto 2);
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signal status_register : std_logic_vector(31 downto 0);
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signal rx_fifo_read : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_data : std_logic_vector(7 downto 0);
signal rx_fifo_usage : integer range 0 to 2047;
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begin
trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
generic map(
F_CLK => F_CLK,
F_CLK_PHY => F_CLK_PHY
)
port map(
clk => clk,
phy_clk => phy_clk,
rst => rst,
phy_out => phy_out,
phy_in => phy_in,
rx_p => rx_p,
tx_p => tx_p,
tx_n => tx_n
);
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rx_fifo_inst : entity generics.fifo_block
generic map(
SIZE => 2047
)
port map(
clk => clk,
rst_a => '0',
clr => rst,
data_in => phy_out.rx_data,
write => phy_out.rx_data_valid,
commit => not phy_out.rx_active,
abort => '0',
full => rx_fifo_full,
data_out => rx_fifo_data,
data_first => open,
empty => rx_fifo_empty,
read => rx_fifo_read,
usage => rx_fifo_usage
);
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wb_adr <= unsigned(wb_i.adr(wb_adr'range));
wbif : process(clk, rst) is
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variable bytes_rxd : unsigned(15 downto 0);
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begin
if rst then
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wb_o.ack <= '0';
rx_fifo_read <= '0';
bytes_rxd := (others => '0');
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elsif rising_edge(clk) then
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wb_o.ack <= '0';
rx_fifo_read <= '0';
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if (phy_out.rx_data_valid = '1') then
bytes_rxd := bytes_rxd + 1;
end if;
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if (wb_i.cyc and wb_i.stb) then
wb_o.ack <= '1';
if wb_adr = 0 then
wb_o.dat <= status_register;
else
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wb_o.dat <= (others => '0');
if wb_o.ack = '0' then
rx_fifo_read <= '1';
end if;
wb_o.dat(7 downto 0) <= rx_fifo_data;
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end if;
end if;
end if;
end process wbif;
wb_o.err <= '0';
wb_o.rty <= '1';
wb_o.stall <= '0';
phy_in.tx_data_en <= '0';
phy_in.tx_data <= (others => '0');
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status_register <= (x"0000" & x"000" & "000" & phy_out.carrier_detect);
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end architecture RTL;