trashernet-soc/fpga/hdl/bench/bench_fifo_block.vhd

-- -------------------------------------------------------------------------- --
--              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
-- -------------------------------------------------------------------------- --
-- TODO
-- -------------------------------------------------------------------------- --
-- Author       : Markus Koch <markus@notsyncing.net>
-- Contributors : None
-- License      : Mozilla Public License (MPL) Version 2
-- -------------------------------------------------------------------------- --

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library generics;
use generics.all;

entity bench_fifo_block is
end entity bench_fifo_block;

architecture RTL of bench_fifo_block is
	signal clk        : std_logic;
	signal rst_a      : std_logic;
	signal clr        : std_logic;
	signal data_in    : std_logic_vector(7 downto 0);
	signal write      : std_logic;
	signal commit     : std_logic;
	signal abort      : std_logic;
	signal full       : std_logic;
	signal data_out   : std_logic_vector(data_in'range);
	signal data_first : std_logic;
	signal empty      : std_logic;
	signal read       : std_logic;

begin
	fifo_block_inst : entity generics.fifo_block
		generic map(
			SIZE => 15
		)
		port map(
			clk        => clk,
			rst_a      => rst_a,
			clr        => clr,
			data_in    => data_in,
			write      => write,
			commit     => commit,
			abort      => abort,
			full       => full,
			data_out   => data_out,
			data_first => data_first,
			empty      => empty,
			read       => read
		);

	clock_driver : process
		constant period : time := 10 ns;
	begin
		clk <= '0';
		wait for period / 2;
		clk <= '1';
		wait for period / 2;
	end process clock_driver;

	test : process is
		procedure push(constant data : in std_logic_vector(7 downto 0)) is
		begin
			data_in <= data;
			write   <= '1';
			wait until rising_edge(clk);
			write   <= '0';
		end procedure push;

		procedure pop(expected : std_logic_vector(7 downto 0); first : boolean) is
		begin
			read <= '1';
			wait until rising_edge(clk);
			report "Read data: " & to_hstring(data_out) & " - " & std_logic'image(data_first);
			assert (data_first = '1') = first report "Data first was " & std_logic'image(data_first) & " instead of " & boolean'image(first);
			assert data_out = expected report "Data is " & to_hstring(data_out) & ", should be " & to_hstring(expected) severity error;
			read <= '0';
		end procedure;

		procedure commit_data is
		begin
			commit <= '1';
			wait until rising_edge(clk);
			commit <= '0';
		end procedure commit_data;
	begin
		rst_a  <= '1';
		clr    <= '0';
		write  <= '0';
		commit <= '0';
		abort  <= '0';
		read   <= '0';

		wait for 10 ns;
		rst_a <= '0';
		wait until rising_edge(clk);

		report "Pushing 5 items into FIFO";
		for i in 1 to 5 loop
			push(std_logic_vector(to_unsigned(i, data_in'length)));
			assert empty = '1' report "FIFO data present without commit";
		end loop;

		report "Committing data";
		commit_data;
		wait until rising_edge(clk);
		assert empty = '0' report "Commit did not validate data";

		report "Reading data";
		for i in 1 to 1 loop
			pop(std_logic_vector(to_unsigned(i, data_in'length)), i = 1);
		end loop;

		std.env.stop(0);
		wait;
	end process test;

end architecture RTL;