89 lines
2.8 KiB
VHDL
89 lines
2.8 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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package ice40_components is
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component SB_PLL40_PAD
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generic(
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FEEDBACK_PATH : string;
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DIVR : std_logic_vector(3 downto 0);
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DIVF : std_logic_vector(6 downto 0);
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DIVQ : std_logic_vector(2 downto 0);
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FILTER_RANGE : std_logic_vector(2 downto 0)
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);
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port(
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RESETB : in std_logic;
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BYPASS : in std_logic;
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PACKAGEPIN : in std_logic;
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PLLOUTCORE : out std_logic
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);
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end component SB_PLL40_PAD;
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component SB_PLL40_CORE
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generic(
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FEEDBACK_PATH : string := "SIMPLE";
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-- DELAY_ADJUSTMENT_MODE_FEEDBACK : string := "FIXED";
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-- DELAY_ADJUSTMENT_MODE_RELATIVE : string := "FIXED";
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-- PLLOUT_SELECT : string := "GENCLK";
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-- SHIFTREG_DIV_MODE : std_logic;
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-- FDA_FEEDBACK : std_logic_vector(3 downto 0) := "1111";
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-- FDA_RELATIVE : std_logic_vector(3 downto 0) := "1111";
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DIVR : std_logic_vector(3 downto 0);
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DIVF : std_logic_vector(6 downto 0);
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DIVQ : std_logic_vector(2 downto 0);
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FILTER_RANGE : std_logic_vector(2 downto 0)
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-- ENABLE_ICEGATE : std_logic := '0';
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-- TEST_MODE : std_logic := '0'
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);
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port(
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REFERENCECLK : in std_logic;
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-- PLLOUTCORE : out std_logic;
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PLLOUTGLOBAL : out std_logic;
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-- EXTFEEDBACK : in std_logic;
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-- DYNAMICDELAY : in std_logic_vector(7 downto 0);
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LOCK : out std_logic;
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BYPASS : in std_logic;
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RESETB : in std_logic
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-- LATCHINPUTVALUE : in std_logic;
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-- SDO : out std_logic;
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-- SDI : in std_logic;
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-- SCLK : in std_logic
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);
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end component SB_PLL40_CORE;
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component SB_HFOSC
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generic(
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CLKHF_DIV : string
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);
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port(
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CLKHFPU : in std_logic;
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CLKHFEN : in std_logic;
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CLKHF : out std_logic
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);
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end component SB_HFOSC;
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COMPONENT SB_IO IS
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GENERIC(
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PIN_TYPE : std_logic_vector(5 downto 0) := "000000";
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IO_STANDARD : string := "SB_LVDS_INPUT"
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);
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PORT(
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PACKAGE_PIN : in std_logic;
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LATCH_INPUT_VALUE : in std_logic;
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CLOCK_ENABLE : in std_logic;
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INPUT_CLK : in std_logic;
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OUTPUT_CLK : in std_logic;
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OUTPUT_ENABLE : in std_logic;
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D_OUT_0 : in std_logic;
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D_OUT_1 : in std_logic;
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D_IN_0 : out std_logic;
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D_IN_1 : out std_logic
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);
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END COMPONENT SB_IO;
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component SB_GB
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port(
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USER_SIGNAL_TO_GLOBAL_BUFFER : in std_logic;
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GLOBAL_BUFFER_OUTPUT : out std_logic);
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end component;
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end package ice40_components;
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