97 lines
2.8 KiB
VHDL
97 lines
2.8 KiB
VHDL
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.round;
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entity uart_tx is
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generic(
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F_CLK : integer := 50_000_000; -- System clock speed
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BAUD_RATE : integer := 115_200 -- Desired baudrate
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);
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port(
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clk : in std_logic; -- System clock @ F_CLK
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rst_a : in std_logic; -- Asynchronous reset
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data : in std_logic_vector; -- Data to send (width determines width of UART payload)
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data_valid : in std_logic; -- Data is valid, TX at next opportunity
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data_latched : out std_logic; -- The data word has been latched, go ahead and apply the next one, or negate data_valid to end the transaction after the current word
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busy : out std_logic; -- The core is busy transmitting a data word
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serial_out : out std_logic -- UART TX line
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);
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end entity uart_tx;
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architecture rtl of uart_tx is
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constant COUNTER_MAX : natural := 10;
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signal sr : std_logic_vector((data'length + 1) - 1 downto 0);
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signal bit_cnt : integer range 0 to COUNTER_MAX;
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constant BITCLK_MAX : integer := integer(real(F_CLK) / real(BAUD_RATE));
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signal bitclk_cnt : integer range 0 to BITCLK_MAX;
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signal bit_stb : std_logic;
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begin
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tx_fsm : process(clk, rst_a) is
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begin
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if (rst_a = '1') then
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sr <= (others => '1');
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bit_cnt <= 0;
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data_latched <= '0';
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elsif (rising_edge(clk)) then
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data_latched <= '0';
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if ((bit_stb = '1') or (bit_cnt = 0)) then
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sr <= '1' & sr(sr'high downto 1);
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if (bit_cnt = 0) then
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if (data_valid = '1') then
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data_latched <= '1';
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sr <= data & '0';
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bit_cnt <= COUNTER_MAX;
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end if;
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else
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bit_cnt <= bit_cnt - 1;
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end if;
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end if;
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end if;
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end process tx_fsm;
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serial_out <= sr(0); -- @suppress PID1: Not a readback signal
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busy <= '1' when (bit_cnt /= 0) or (data_valid = '1') else '0';
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bitclk : process(clk, rst_a) is
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begin
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if rst_a then
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bit_stb <= '0';
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bitclk_cnt <= BITCLK_MAX;
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elsif rising_edge(clk) then
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bit_stb <= '0';
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if not busy then
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bitclk_cnt <= BITCLK_MAX;
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else
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if bitclk_cnt = 0 then
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bitclk_cnt <= BITCLK_MAX;
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bit_stb <= '1';
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else
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bitclk_cnt <= bitclk_cnt - 1;
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end if;
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end if;
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end if;
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end process bitclk;
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end architecture rtl;
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