electronics/trashernet-soc
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env: Replace build script with proper Makefile

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This commit is contained in:
Markus Koch 2024-07-06 19:15:20 +02:00
parent dd7cf08b6f
commit 434a06fa70
2 changed files with 68 additions and 43 deletions
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68
fpga/Makefile Normal file
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# -------------------------------------------------------------------------- --
# TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
# -------------------------------------------------------------------------- --
# TODO
# -------------------------------------------------------------------------- --
# Author : Markus Koch <markus@notsyncing.net>
# Contributors : None
# License : Mozilla Public License (MPL) Version 2
# -------------------------------------------------------------------------- --
BUILD_DIR=./build
VU_DIR=$(BUILD_DIR)/vunit_out
VU_FLAG=$(VU_DIR)/flag
# Collect VHDL sources using VUnit
SOURCES_VHDL=$(shell ./run.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')
# Collect Verilog sources using bash
SERV_DIR=hdl/serv
SOURCES_VERILOG=$(SERV_DIR)/rtl/*.v
SOURCES_VERILOG+=$(SERV_DIR)/servant/servant_ram.v $(SERV_DIR)/servant/servant_timer.v
# Miscellaneous sources that when changed must trigger a rebuild
SOURCES_MISC=../sw/bootrom/bootrom.vhex
# Constraints
CONSTRAINTS=constraints.pcf
# HW Settings
YOSYS_DEVICE=u
DEVICE?=--up5k # --up5k, --u4k
PACKAGE?=sg48
# Programmer Settings
PROGRAMMER=ft2232
# ---------------------------------------------------------------------------- #
default: $(BUILD_DIR)/bitstream.bin
$(VU_FLAG): $(SOURCES_VHDL) $(SOURCES_MISC)
./run.py --compile -o $(VU_DIR)
touch $@
$(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
# Collect GHDL sources from VUnit
$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
nextpnr-ice40 $(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
$(BUILD_DIR)/bitstream.bin: $(BUILD_DIR)/netlist-post-pnr.asc
icepack $< $@
flash: $(BUILD_DIR)/bitstream.bin
openFPGALoader --unprotect-flash -f -c $(PROGRAMMER) -b ice40_generic $<
clean:
rm -r $(BUILD_DIR)
.phony: flash clean
# Useful aliases
compile_vhdl: $(VU_FLAG)
synth: $(BUILD_DIR)/netlist-post-synthesis.json
pnr: $(BUILD_DIR)/netlist-post-pnr.asc
pack: $(BUILD_DIR)/bitstream.bin

43
fpga/build.sh
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#!/bin/bash
# -------------------------------------------------------------------------- --
# TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
# -------------------------------------------------------------------------- --
# TODO
# -------------------------------------------------------------------------- --
# Author : Markus Koch <markus@notsyncing.net>
# Contributors : None
# License : Mozilla Public License (MPL) Version 2
# -------------------------------------------------------------------------- --
if [ "$1" == "flash" ]; then
openFPGALoader --unprotect-flash -f -c ft2232 -b ice40_generic build/bitstream.bin
exit 0
fi
mkdir -p build
cd build
set -e
../run.py --compile
BASEDIR=".."
DEVICE=--up5k # --up5k, --u4k
PACKAGE=sg48
# Collect pre-analyzed VHDL sources
GHDLINCDIRS=`find ./vunit_out/ghdl/libraries -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '`
# Collect Verilog sources
SERV="$BASEDIR/hdl/serv"
VLOGS=`echo ../hdl/serv/rtl/*.v`
VLOGS="$VLOGS $SERV/servant/servant_ram.v $SERV/servant/servant_timer.v"
# Synthesize and PnR
# -device <hx | lp | u>
yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
nextpnr-ice40 $DEVICE --package $PACKAGE --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf
# Generate bitstream
icepack netlist.asc bitstream.bin