fpga: Cleanly separate build VUnit from bench VUnit

fpga/.gitignore

@@ -1,2 +1,4 @@
 build/**
 *.bak
+wave.fst
+vunit_out

fpga/Makefile

@@ -13,7 +13,7 @@ VU_DIR=$(BUILD_DIR)/vunit_out
 VU_FLAG=$(VU_DIR)/flag
 
 # Collect VHDL sources using VUnit
-SOURCES_VHDL=$(shell ./run.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')
+SOURCES_VHDL=$(shell VUNIT_SIMULATOR=ghdl ./run_physical.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')
 
 # Collect Verilog sources using bash
 SERV_DIR=hdl/serv
@@ -39,7 +39,7 @@ PROGRAMMER=ft2232
 default: $(BUILD_DIR)/bitstream.bin
 
 $(VU_FLAG): $(SOURCES_VHDL) $(SOURCES_MISC)
-	./run.py --compile -o $(VU_DIR)
+	VUNIT_SIMULATOR=ghdl ./run_physical.py --compile -o $(VU_DIR)
 	touch $@
 
 $(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
@@ -60,9 +60,16 @@ flash: $(BUILD_DIR)/bitstream.bin
 	openFPGALoader --unprotect-flash -f -c $(PROGRAMMER) -b ice40_generic $<
 
 clean:
-	rm -r $(BUILD_DIR)
+	# Build artifacts
+	rm -rf $(BUILD_DIR)
+	# Simulation artifacts
+	rm -rf vunit_out
+	rm -rf wave.fst*
 
-.phony: flash clean
+simulation:
+	./run.py
+
+.phony: flash clean simulation
 
 # Useful aliases
 compile_vhdl: $(VU_FLAG)

fpga/run.py

@@ -23,7 +23,7 @@ project_dir=pathlib.Path(__file__).parent.resolve()
 libs = {}
 
 vu = VUnit.from_argv(compile_builtins=False)
-#vu.add_vhdl_builtins()
+vu.add_vhdl_builtins()
 
 for base_path in libraries:
 	for library_name in libraries[base_path]:
@@ -47,11 +47,12 @@ for base_path in libraries:
 					libs[library_name].add_source_files(path)
 
 # If we don't already use our own OSVVM implementation, add the default one.
-#if not "osvvm" in libs:
+if not "osvvm" in libs:
-#	vu.add_osvvm()
+	vu.add_osvvm()
 
 vu.add_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys"])
 vu.add_compile_option("nvc.a_flags", ["--relaxed"])
 #vu.set_sim_option("nvc.elab_flags", ["-O3"])
+vu.set_sim_option("nvc.sim_flags", ["--format=fst", "--wave=wave.fst"])
 
 vu.main()

fpga/run_physical.py

@@ -0,0 +1,56 @@
+#!/usr/bin/env python
+
+from vunit import VUnit
+import os
+import pathlib
+import subprocess
+import pathlib
+
+libraries = {
+	# Design files
+	os.path.realpath(os.path.join(__file__, "..")) : {
+		"design",
+		"device_models",
+		"generics",
+		"serv",
+		"trashernet"
+	}
+}
+
+project_dir=pathlib.Path(__file__).parent.resolve()
+
+libs = {}
+
+vu = VUnit.from_argv(compile_builtins=False)
+#vu.add_vhdl_builtins()
+
+for base_path in libraries:
+	for library_name in libraries[base_path]:
+		libs[library_name] = vu.add_library(library_name)
+
+		if type(libraries[base_path]) is dict: # Manually specified files
+			print("direct")
+			for filename in libraries[base_path][library_name]:
+				libs[library_name].add_source_files(os.path.join(base_path, filename))
+		else: # Auto-detect files
+			print(f"Importing: {library_name}")
+			if library_name == "trashernet": # Special case: Trashernet submodule
+				path = os.path.join(base_path, "hdl", library_name, library_name, "*.vhd")
+				libs[library_name].add_source_files(path)
+			elif library_name == "serv": # Special case: SERV submodule
+				print("Skipping SERV. It's Verilog.")
+			else: # Normal lib
+				path = os.path.join(base_path, "hdl", library_name)
+				if os.path.exists(path):
+					path=os.path.join(path, "*.vhd")
+					libs[library_name].add_source_files(path)
+
+# If we don't already use our own OSVVM implementation, add the default one.
+#if not "osvvm" in libs:
+#	vu.add_osvvm()
+
+vu.add_compile_option("ghdl.a_flags", ["-frelaxed", "-fsynopsys"])
+vu.add_compile_option("nvc.a_flags", ["--relaxed"])
+#vu.set_sim_option("nvc.elab_flags", ["-O3"])
+
+vu.main()