fpga: ram: Use Verilog model for synthesis and VHDL for simulation
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fpga/hdl/design/ram_vhdl.vhd
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94
fpga/hdl/design/ram_vhdl.vhd
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- Servant-compatible RAM, rewritten in VHDL
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library generics;
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use generics.wishbone_pkg.all;
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entity ram_vhdl is
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generic(
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memfile : string := "data/empty.hex";
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read_only : boolean := false;
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adr_width : integer := 16
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);
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port(
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clk : in std_logic; -- CPU and bus clock
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clr : in std_logic; -- Synchronous reset
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wb_o : out wishbone_slave_out; -- Wishbone bus (out)
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wb_i : in wishbone_slave_in -- Wishbone bus (in)
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);
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end entity ram_vhdl;
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architecture rtl of ram_vhdl is
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type mem_t is array (0 to 2 ** adr_width - 1) of std_logic_vector(wb_i.dat'range);
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impure function init_ram_hex return mem_t is
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file text_file : text open read_mode is memfile;
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variable text_line : line;
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variable ram_content : mem_t := (others => (others => '0'));
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begin
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for i in 0 to 2 ** adr_width - 1 loop
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exit when endfile(text_file);
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readline(text_file, text_line);
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hread(text_line, ram_content(i));
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end loop;
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return ram_content;
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end function;
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signal mem : mem_t := init_ram_hex;
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signal mem_address : integer range mem'range;
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begin
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wb_o.rty <= '0';
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wb_o.err <= '0';
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wb_o.stall <= '0';
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mem_address <= to_integer(unsigned(wb_i.adr(adr_width - 1 + 2 downto 2)));
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rowarn : process(clk) is
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begin
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if rising_edge(clk) then
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if wb_i.cyc and wb_i.stb then
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if (unsigned(wb_i.adr) > 2 ** adr_width - 1) then
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report "ERROR: Out of bounds for " & ram_vhdl'path_name & " @0x" & to_hstring(wb_i.adr) severity error;
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end if;
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if (wb_i.we = '1' and read_only) then
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report "ERROR: Write access to ROM @0x" & to_hstring(wb_i.adr) severity warning;
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end if;
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end if;
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end if;
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end process rowarn;
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mem_p : process(clk) is
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begin
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if rising_edge(clk) then
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wb_o.dat <= mem(mem_address);
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wb_o.ack <= wb_i.stb;
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if (wb_i.we) then
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wb_o.dat <= (others => '-');
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for i in wb_i.sel'range loop
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if wb_i.sel(i) then
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mem(mem_address)((i + 1) * 8 - 1 downto (i * 8)) <= wb_i.dat((i + 1) * 8 - 1 downto (i * 8));
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end if;
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end loop;
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end if;
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if clr then
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wb_o.dat <= (others => '-');
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wb_o.ack <= '0';
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end if;
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end if;
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end process mem_p;
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end architecture rtl;
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@ -1,7 +1,7 @@
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-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- Servant-compatible RAM, rewritten in VHDL
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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@ -11,7 +11,6 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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library generics;
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use generics.wishbone_pkg.all;
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@ -20,7 +19,8 @@ entity servant_ram_vhdl is
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generic(
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memfile : string := "data/empty.hex";
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read_only : boolean := false;
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adr_width : integer := 16
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adr_width : integer := 16;
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force_vlog : boolean := false
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);
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port(
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clk : in std_logic; -- CPU and bus clock
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@ -32,31 +32,49 @@ entity servant_ram_vhdl is
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end entity servant_ram_vhdl;
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architecture rtl of servant_ram_vhdl is
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type mem_t is array (0 to 2 ** adr_width - 1) of std_logic_vector(wb_i.dat'range);
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component servant_ram
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generic(
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depth : integer;
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aw : integer;
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memfile : string
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);
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port(
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i_wb_clk : in std_logic;
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i_wb_rst : in std_logic;
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i_wb_adr : in std_logic_vector;
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i_wb_dat : in std_logic_vector;
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i_wb_sel : in std_logic_vector;
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i_wb_we : in std_logic;
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i_wb_cyc : in std_logic;
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o_wb_rdt : out std_logic_vector;
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o_wb_ack : out std_logic
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);
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end component servant_ram;
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impure function init_ram_hex return mem_t is
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file text_file : text open read_mode is memfile;
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variable text_line : line;
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variable ram_content : mem_t := (others => (others => '0'));
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begin
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for i in 0 to 2 ** adr_width - 1 loop
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exit when endfile(text_file);
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readline(text_file, text_line);
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hread(text_line, ram_content(i));
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end loop;
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vlogforce : if force_vlog generate
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servant_ram_inst : component servant_ram
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generic map(
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depth => 2 ** adr_width,
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aw => adr_width,
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memfile => memfile
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)
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port map(
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i_wb_clk => clk,
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i_wb_rst => clr,
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i_wb_adr => wb_i.adr(adr_width - 1 downto 2),
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i_wb_dat => wb_i.dat,
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i_wb_sel => wb_i.sel,
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i_wb_we => wb_i.we,
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i_wb_cyc => wb_i.cyc and wb_i.stb,
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o_wb_rdt => wb_o.dat,
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o_wb_ack => wb_o.ack
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);
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return ram_content;
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end function;
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signal mem : mem_t := init_ram_hex;
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signal mem_address : integer range mem'range;
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begin
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wb_o.rty <= '0';
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wb_o.err <= '0';
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wb_o.stall <= '0';
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mem_address <= to_integer(unsigned(wb_i.adr(adr_width - 1 + 2 downto 2)));
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rowarn : process(clk) is
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begin
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if rising_edge(clk) then
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@ -71,24 +89,18 @@ begin
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end if;
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end process rowarn;
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mem_p : process(clk) is
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begin
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if rising_edge(clk) then
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wb_o.dat <= mem(mem_address);
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wb_o.ack <= wb_i.stb;
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if (wb_i.we) then
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wb_o.dat <= (others => '-');
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for i in wb_i.sel'range loop
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if wb_i.sel(i) then
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mem(mem_address)((i + 1) * 8 - 1 downto (i * 8)) <= wb_i.dat((i + 1) * 8 - 1 downto (i * 8));
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end if;
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end loop;
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end if;
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if clr then
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wb_o.dat <= (others => '-');
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wb_o.ack <= '0';
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end if;
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end if;
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end process mem_p;
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else generate
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ram_vhdl_inst : entity work.ram_vhdl
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generic map(
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memfile => memfile,
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read_only => read_only,
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adr_width => adr_width
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)
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port map(
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clk => clk,
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clr => clr,
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wb_o => wb_o,
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wb_i => wb_i
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);
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end generate vlogforce;
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end architecture rtl;
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@ -239,7 +239,8 @@ begin
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generic map(
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memfile => "../sw/bootrom/bootrom.vhex",
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read_only => true,
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adr_width => 9
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adr_width => 9,
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force_vlog => not in_simulation -- GHDL + Yosys doesn't keep the memfile
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)
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port map(
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clk => clk,
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