electronics/trashernet-soc
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fpga: Clean up clocking code

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This commit is contained in:
Markus Koch 2024-08-09 13:43:35 +02:00
parent b06ccdda2a
commit e7d9f391ef
4 changed files with 63 additions and 37 deletions
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2
fpga/constraints.pcf
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@ -23,7 +23,7 @@ set_io pmod[7] 31
set_io uart_rx 37
set_io uart_tx 36
set_io clk_50m 35
set_io clk_in 35
#set_io eth_rx_n 38
set_io eth_rx_p 42

45
fpga/hdl/design/pll0.vhd
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@ -16,6 +16,7 @@ use generics.ice40_components.all;
entity pll0 is
generic(
F_IN : in integer;
F_CLK : in integer;
F_CLK_PHY : in integer
);
@ -28,43 +29,29 @@ entity pll0 is
end pll0;
architecture Structure of pll0 is
signal clk_int_osc : std_logic;
signal clk_out_i : std_logic;
begin
SB_HFOSC_inst : component SB_HFOSC
generic map(
CLKHF_DIV => "0b01" -- 24 MHz
)
port map(
CLKHFPU => '1',
CLKHFEN => '1',
CLKHF => clk_int_osc
);
-- SB_PLL40_PAD_inst : component SB_PLL40_PAD
-- generic map(
-- FEEDBACK_PATH => "SIMPLE",
-- DIVR => "0000",
-- DIVF => "1000010",
-- DIVQ => "100",
-- FILTER_RANGE => "001"
-- )
-- port map(
-- RESETB => '1',
-- BYPASS => '0',
-- PACKAGEPIN => clk_in,
-- PLLOUTCORE => clk_out_phy
-- );
clk_out_phy <= clk_in;
-- Not clean, but it works...
ckdiv2 : process(clk_out_phy) is
begin
if rising_edge(clk_out_phy) then
clk_out <= not clk_out;
clk_out_i <= not clk_out_i;
end if;
end process ckdiv2;
SB_GB_inst : component SB_GB
port map(
USER_SIGNAL_TO_GLOBAL_BUFFER => clk_out_i,
GLOBAL_BUFFER_OUTPUT => clk_out
);
SB_GB2_inst : component SB_GB
port map(
USER_SIGNAL_TO_GLOBAL_BUFFER => clk_in,
GLOBAL_BUFFER_OUTPUT => clk_out_phy
);
assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure;
assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;
end Structure;

6
fpga/hdl/design/top.vhd
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@ -20,12 +20,13 @@ use generics.ice40_components.all;
entity top is
generic(
-- System configuration
F_IN : integer := 50000000;
F_CLK : integer := 25000000;
F_CLK_PHY : integer := 50000000;
UART_BAUD : integer := 250000
);
port(
clk_50m : in std_logic; -- System clock
clk_in : in std_logic; -- System clock
-- UART
uart_tx : out std_logic; -- UART TX
@ -173,11 +174,12 @@ begin
else generate
pll_inst : entity work.pll0
generic map(
F_IN => F_IN,
F_CLK => F_CLK,
F_CLK_PHY => F_CLK_PHY
)
port map(
clk_in => clk_50m,
clk_in => clk_in,
clk_out => clk,
clk_out_phy => clk_phy,
locked => pll_locked

41
fpga/hdl/generics/ice40_components.vhd
View File

@ -14,10 +14,47 @@ package ice40_components is
RESETB : in std_logic;
BYPASS : in std_logic;
PACKAGEPIN : in std_logic;
PLLOUTCORE : out std_logic
PLLOUTCORE : out std_logic;
PLLOUTGLOBAL : out std_logic
);
end component SB_PLL40_PAD;
component SB_PLL40_2_PAD
generic(
FEEDBACK_PATH : string;
DIVR : std_logic_vector(3 downto 0);
DIVF : std_logic_vector(6 downto 0);
DIVQ : std_logic_vector(2 downto 0);
FILTER_RANGE : std_logic_vector(2 downto 0)
);
port(
RESETB : in std_logic;
BYPASS : in std_logic;
PACKAGEPIN : in std_logic;
PLLOUTCOREA : out std_logic;
PLLOUTCOREB : out std_logic;
PLLOUTGLOBALA : out std_logic;
PLLOUTGLOBALB : out std_logic
);
end component SB_PLL40_2_PAD;
component SB_PLL40_2_CORE
generic(
FEEDBACK_PATH : string;
DIVR : std_logic_vector(3 downto 0);
DIVF : std_logic_vector(6 downto 0);
DIVQ : std_logic_vector(2 downto 0);
FILTER_RANGE : std_logic_vector(2 downto 0)
);
port(
RESETB : in std_logic;
BYPASS : in std_logic;
REFERENCECLK : in std_logic;
PLLOUTCOREA : out std_logic;
PLLOUTCOREB : out std_logic
);
end component SB_PLL40_2_CORE;
component SB_PLL40_CORE
generic(
FEEDBACK_PATH : string := "SIMPLE";
@ -36,7 +73,7 @@ package ice40_components is
);
port(
REFERENCECLK : in std_logic;
-- PLLOUTCORE : out std_logic;
PLLOUTCORE : out std_logic;
PLLOUTGLOBAL : out std_logic;
-- EXTFEEDBACK : in std_logic;
-- DYNAMICDELAY : in std_logic_vector(7 downto 0);