fpga: Implement functional Ethernet controller
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79b1153df7
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@ -38,8 +38,8 @@ set_io eth_tx_p[1] 2
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set_io eth_tx_p[2] 4
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set_io eth_tx_p[3] 3
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set_io eth_led_green 40
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set_io eth_led_orange 41
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set_io eth_led_green_n 40
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set_io eth_led_orange_n 41
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set_io led_user 34
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@ -38,8 +38,8 @@ entity top is
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eth_tx_n : out std_logic_vector(3 downto 0); -- Ethernet TX-
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-- LEDs
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eth_led_green : out std_logic;
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eth_led_orange : out std_logic;
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eth_led_green_n : out std_logic;
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eth_led_orange_n : out std_logic;
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led_user : out std_logic; --
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-- PSRAM IF
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@ -69,6 +69,9 @@ architecture rtl of top is
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signal eth_tx_n_i : std_logic;
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signal eth_rx_p_i : std_logic;
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signal eth_led_green : std_logic;
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signal eth_led_orange : std_logic;
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-- System Timer
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signal irq_timer : std_logic;
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@ -247,7 +250,9 @@ begin
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wb_i => wb_eth_i,
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rx_p => eth_rx_p_i,
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tx_p => eth_tx_p_i,
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tx_n => eth_tx_n_i
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tx_n => eth_tx_n_i,
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led_rx => eth_led_green,
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led_tx => eth_led_orange
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);
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eth_tx_p <= (others => eth_tx_p_i);
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eth_tx_n <= (others => eth_tx_n_i);
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@ -264,9 +269,9 @@ begin
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mask => wishbone_masks
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);
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eth_led_green <= uart_tx;
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eth_led_orange <= uart_rx;
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led_user <= not psram_ce_n;
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eth_led_green_n <= not eth_led_green;
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eth_led_orange_n <= not eth_led_orange;
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led_user <= not uart_tx or not uart_rx;
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flash_ce_n <= 'Z';
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flash_sclk <= 'Z';
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@ -37,7 +37,10 @@ entity trashernet_phy_wb is
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-- Ethernet physical signals
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic
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tx_n : out std_logic;
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-- LEDs
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led_tx : out std_logic;
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led_rx : out std_logic
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);
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end entity trashernet_phy_wb;
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@ -46,6 +49,9 @@ architecture RTL of trashernet_phy_wb is
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signal phy_out : phy_out_t; -- PHY application IF (out)
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signal phy_in : phy_in_t; -- PHY application IF (in)
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signal mac_out : raw_mac_out_t; -- MAC application IF (out)
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signal mac_in : raw_mac_in_t; -- MAC application IF (in)
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signal wb_adr : unsigned(2 downto 2);
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signal status_register : std_logic_vector(31 downto 0);
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@ -57,6 +63,11 @@ architecture RTL of trashernet_phy_wb is
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signal tx_fifo_commit : std_logic;
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signal tx_fifo_empty : std_logic;
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signal tx_fifo_data : std_logic_vector(7 downto 0);
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signal rx_fifo_empty : std_logic;
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signal rx_bitcount : std_logic_vector(10 downto 0);
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signal rx_fifo_block_count : std_logic_vector(rx_bitcount'range);
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signal rx_block_next : std_logic;
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begin
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trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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@ -74,6 +85,16 @@ begin
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tx_n => tx_n
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);
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trashernet_raw_mac_inst : entity trashernet.trashernet_raw_mac
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port map(
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clk => clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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mac_out => mac_out,
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mac_in => mac_in
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);
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rx_fifo_inst : entity generics.fifo_block
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generic map(
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SIZE => 2047
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@ -82,18 +103,48 @@ begin
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clk => clk,
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rst_a => '0',
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clr => rst,
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data_in => phy_out.rx_data,
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write => phy_out.rx_data_valid,
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commit => not phy_out.rx_active,
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abort => '0',
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data_in => mac_out.rx_mac_data,
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write => mac_out.rx_mac_valid,
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commit => mac_out.rx_mac_crc_ok,
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abort => mac_out.rx_mac_crc_error,
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full => open,
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data_out => rx_fifo_data,
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data_first => open,
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empty => open,
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empty => rx_fifo_empty,
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read => rx_fifo_read,
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usage => open
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);
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fifo_inst : entity generics.fifo
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generic map(
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SIZE => 31
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)
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port map(
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clk => clk,
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rst_a => '0',
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clr => rst,
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data_in => rx_bitcount,
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write => mac_out.rx_mac_crc_ok,
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full => open,
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data_out => rx_fifo_block_count,
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empty => open,
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read => rx_block_next,
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usage => open
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);
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rxcount : process(rst, clk) is
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begin
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if rst then
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rx_bitcount <= (others => '0');
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elsif rising_edge(clk) then
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if mac_out.rx_mac_crc_error or mac_out.rx_mac_crc_ok then
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rx_bitcount <= (others => '0');
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elsif mac_out.rx_mac_valid then
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rx_bitcount <= std_logic_vector(unsigned(rx_bitcount) + 1);
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end if;
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end if;
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end process rxcount;
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tx_fifo_inst : entity generics.fifo_block
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generic map(
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SIZE => 2047
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@ -110,7 +161,7 @@ begin
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data_out => tx_fifo_data,
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data_first => open,
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empty => tx_fifo_empty,
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read => phy_out.tx_data_ack,
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read => mac_out.tx_mac_data_ack,
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usage => open
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);
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@ -122,12 +173,14 @@ begin
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rx_fifo_read <= '0';
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tx_fifo_write <= '0';
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tx_fifo_commit <= '0';
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rx_block_next <= '0';
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elsif rising_edge(clk) then
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wb_o.ack <= '0';
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rx_fifo_read <= '0';
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tx_fifo_write <= '0';
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tx_fifo_commit <= '0';
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rx_block_next <= '0';
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if (wb_i.cyc and wb_i.stb) then
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wb_o.ack <= '1';
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@ -136,7 +189,8 @@ begin
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wb_o.dat <= status_register;
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if wb_o.ack = '0' then
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if wb_i.we = '1' then
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tx_fifo_commit <= '1';
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tx_fifo_commit <= wb_i.dat(2);
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rx_block_next <= wb_i.dat(1);
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end if;
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end if;
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else
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@ -159,8 +213,43 @@ begin
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wb_o.rty <= '1';
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wb_o.stall <= '0';
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phy_in.tx_data_en <= not tx_fifo_empty; -- FIXME: this does not care about inter-packet gaps indicated by `data_first`
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phy_in.tx_data <= tx_fifo_data;
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mac_in.tx_mac_data_en <= not tx_fifo_empty; -- FIXME: this does not care about inter-packet gaps indicated by `data_first`
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mac_in.tx_mac_data <= tx_fifo_data;
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status_register <= (x"0000" & x"000" & "000" & phy_out.carrier_detect);
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status_register <= ("0" & x"0" & rx_fifo_block_count & -- 31..16
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x"000" & "0" & (not tx_fifo_empty) & (not rx_fifo_empty) & phy_out.carrier_detect);
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ledstretch : process(clk) is
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constant CMAX : integer := integer(0.2 / (1.0 / real(F_CLK)));
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variable cnt : integer range 0 to CMAX;
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begin
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if rising_edge(clk) then
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if cnt = 0 then
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led_rx <= phy_out.carrier_detect;
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if phy_out.rx_active then
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cnt := CMAX;
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end if;
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else
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led_rx <= '0';
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cnt := cnt - 1;
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end if;
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end if;
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end process ledstretch;
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ledstretch2 : process(clk) is
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constant CMAX : integer := integer(0.2 / (1.0 / real(F_CLK)));
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variable cnt : integer range 0 to CMAX;
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begin
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if rising_edge(clk) then
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if cnt = 0 then
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led_tx <= '0';
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if phy_out.tx_active then
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cnt := CMAX;
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end if;
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else
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led_tx <= '1';
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cnt := cnt - 1;
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end if;
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end if;
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end process ledstretch2;
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end architecture RTL;
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@ -1 +1 @@
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Subproject commit 21a0d0e69aeacf9747bfac0262e0d7ca30a691d9
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Subproject commit 206332f3d1c1f5b704bad09b1380a8aed8b736aa
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