|
|
cc4b088173
|
fpga: ram: Use Verilog model for synthesis and VHDL for simulation
|
2024-09-27 16:34:55 +02:00 |
|
|
|
7497f1f6bb
|
fpga: Add Sigasi / Code project
|
2024-09-27 14:47:45 +02:00 |
|
|
|
ba299e537b
|
fpga: Add NEORV32 as alternative CPU core
|
2024-09-27 14:44:28 +02:00 |
|
|
|
e7d9f391ef
|
fpga: Clean up clocking code
|
2024-08-09 14:01:16 +02:00 |
|
|
|
b06ccdda2a
|
fpga: Update UART baud rate to 250 kbaud/s
|
2024-08-09 11:31:59 +02:00 |
|
|
|
74280fb79a
|
fpga: Implement single-instruction prefetching from external RAM
|
2024-08-01 21:06:14 +02:00 |
|
|
|
e81166a82c
|
fpga: Implement functional Ethernet controller
|
2024-07-23 19:13:42 +02:00 |
|
|
|
dd7cf08b6f
|
fpga: Continue work on full HW support
|
2024-07-06 19:14:39 +02:00 |
|
|
|
b7c1286d76
|
fpga: Implement basic SERV SoC
|
2024-06-22 11:28:15 +02:00 |
|
