3 Commits

Author	SHA1	Message	Date
Markus Koch	cc4b088173	fpga: ram: Use Verilog model for synthesis and VHDL for simulation	2024-09-27 16:34:55 +02:00
Markus Koch	bb7b2a7a10	fpga: servant_ram: Rewrite in VHDL	2024-09-27 14:42:38 +02:00
Markus Koch	b7c1286d76	fpga: Implement basic SERV SoC	2024-06-22 11:28:15 +02:00