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base: electronics:838a8abe7b636277e398e0ffd9faa6b2c677cd34
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electronics:master
electronics:feature/fpga
electronics:rev-1.0
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compare: electronics:f9335f202e89ee125ab6aa25afa177fd782afa46
Branches Tags
electronics:feature/fpga
electronics:master
electronics:rev-1.0

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838a8abe7b ... f9335f202e

Author SHA1 Message Date
Markus Koch
f9335f202e fpga: Clean up clocking code 2024-08-09 13:43:35 +02:00
2 changed files with 3 additions and 8 deletions
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9
fpga/hdl/design/pll0.vhd
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@ -29,7 +29,8 @@ entity pll0 is
end pll0; end pll0;
architecture Structure of pll0 is architecture Structure of pll0 is
signal clk_out_i : std_logic; signal clk_int_osc : std_logic;
signal clk_out_i : std_logic;
begin begin
-- Not clean, but it works... -- Not clean, but it works...
ckdiv2 : process(clk_out_phy) is ckdiv2 : process(clk_out_phy) is
@ -45,12 +46,6 @@ begin
GLOBAL_BUFFER_OUTPUT => clk_out GLOBAL_BUFFER_OUTPUT => clk_out
); );
SB_GB2_inst : component SB_GB
port map(
USER_SIGNAL_TO_GLOBAL_BUFFER => clk_in,
GLOBAL_BUFFER_OUTPUT => clk_out_phy
);
assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure; assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure;
assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure; assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure; assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;

2
tools/flash.py
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@ -56,7 +56,7 @@ def get_diff(a, b):
def probe(): def probe():
r = sread(0, 4, quiet = True); r = sread(0, 4, quiet = True);
if r is None: if r != b'7\x03\x00\x81':
eprint("ERROR: Probe failed! Check that the device is in bootloader mode.") eprint("ERROR: Probe failed! Check that the device is in bootloader mode.")
return 1 return 1
return 0 return 0