fpga: Clean up clocking code

fpga/hdl/design/pll0.vhd

@@ -29,6 +29,7 @@ entity pll0 is
 end pll0;
 
 architecture Structure of pll0 is
+	signal clk_int_osc : std_logic;
 	signal clk_out_i   : std_logic;
 begin
 	-- Not clean, but it works...
@@ -45,12 +46,6 @@ begin
 			GLOBAL_BUFFER_OUTPUT         => clk_out
 		);
 
-	SB_GB2_inst : component SB_GB
-		port map(
-			USER_SIGNAL_TO_GLOBAL_BUFFER => clk_in,
-			GLOBAL_BUFFER_OUTPUT         => clk_out_phy
-		);
-
 	assert F_IN = 50000000 report "clk_in: PLL expects clock different from specified." severity failure;
 	assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
 	assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;

tools/flash.py

@@ -56,7 +56,7 @@ def get_diff(a, b):
 
 def probe():
 	r = sread(0, 4, quiet = True);
-	if r is None:
+	if r != b'7\x03\x00\x81':
 		eprint("ERROR: Probe failed! Check that the device is in bootloader mode.")
 		return 1
 	return 0