electronics/trashernet-soc
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base: electronics:b06ccdda2a3fb64e2b1c5a011e32bcac0092f32d
Branches Tags
electronics:master
electronics:feature/fpga
electronics:rev-1.0
..
compare: electronics:e561c31691ea0b5385e60f0169b5d90ab2e3ef10
Branches Tags
electronics:feature/fpga
electronics:master
electronics:rev-1.0

No commits in common. "b06ccdda2a3fb64e2b1c5a011e32bcac0092f32d" and "e561c31691ea0b5385e60f0169b5d90ab2e3ef10" have entirely different histories.
b06ccdda2a ... e561c31691

3 changed files with 3 additions and 5 deletions
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2
fpga/hdl/design/top.vhd
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@ -22,7 +22,7 @@ entity top is
-- System configuration -- System configuration
F_CLK : integer := 25000000; F_CLK : integer := 25000000;
F_CLK_PHY : integer := 50000000; F_CLK_PHY : integer := 50000000;
UART_BAUD : integer := 250000 UART_BAUD : integer := 19200
); );
port( port(
clk_50m : in std_logic; -- System clock clk_50m : in std_logic; -- System clock

4
fpga/hdl/design/uart_wb.vhd
View File

@ -41,7 +41,6 @@ architecture rtl of uart_wb is
signal status_register : std_logic_vector(31 downto 0); signal status_register : std_logic_vector(31 downto 0);
signal in_data : std_logic_vector(7 downto 0); signal in_data : std_logic_vector(7 downto 0);
signal in_data_latched : std_logic_vector(in_data'range);
signal in_data_valid : std_logic; signal in_data_valid : std_logic;
signal in_data_available : std_logic; signal in_data_available : std_logic;
@ -105,7 +104,7 @@ begin
out_data <= wb_i.dat(out_data'range); out_data <= wb_i.dat(out_data'range);
out_data_valid <= '1'; out_data_valid <= '1';
else else
wb_o.dat <= x"000000" & in_data_latched; wb_o.dat <= x"000000" & in_data;
in_data_available <= '0'; in_data_available <= '0';
end if; end if;
end if; end if;
@ -113,7 +112,6 @@ begin
if in_data_valid then if in_data_valid then
in_data_available <= '1'; in_data_available <= '1';
in_data_latched <= in_data;
end if; end if;
end if; end if;
end process wb_if; end process wb_if;

2
tools/flash.py
View File

@ -17,7 +17,7 @@ from ast import literal_eval
def eprint(*args, **kwargs): def eprint(*args, **kwargs):
print(*args, file=sys.stderr, **kwargs) print(*args, file=sys.stderr, **kwargs)
ser = serial.Serial('/dev/ttyUSB0', 250000, timeout=2) ser = serial.Serial('/dev/ttyUSB0', 19200, timeout=2)
def sread(address, length, quiet = False): def sread(address, length, quiet = False):
if not quiet: if not quiet: