fpga/hdl/design/top.vhd

@@ -22,7 +22,7 @@ entity top is
 		-- System configuration
 		F_CLK     : integer := 25000000;
 		F_CLK_PHY : integer := 50000000;
-		UART_BAUD : integer := 250000
+		UART_BAUD : integer := 19200
 	);
 	port(
 		clk_50m          : in    std_logic; -- System clock

fpga/hdl/design/uart_wb.vhd

@@ -41,7 +41,6 @@ architecture rtl of uart_wb is
 	signal status_register : std_logic_vector(31 downto 0);
 
 	signal in_data           : std_logic_vector(7 downto 0);
-	signal in_data_latched   : std_logic_vector(in_data'range);
 	signal in_data_valid     : std_logic;
 	signal in_data_available : std_logic;
 
@@ -105,7 +104,7 @@ begin
 						out_data       <= wb_i.dat(out_data'range);
 						out_data_valid <= '1';
 					else
-						wb_o.dat          <= x"000000" & in_data_latched;
+						wb_o.dat          <= x"000000" & in_data;
 						in_data_available <= '0';
 					end if;
 				end if;
@@ -113,7 +112,6 @@ begin
 
 			if in_data_valid then
 				in_data_available <= '1';
-				in_data_latched   <= in_data;
 			end if;
 		end if;
 	end process wb_if;

tools/flash.py

@@ -17,7 +17,7 @@ from ast import literal_eval
 def eprint(*args, **kwargs):
 	print(*args, file=sys.stderr, **kwargs)
 
-ser = serial.Serial('/dev/ttyUSB0', 250000, timeout=2)
+ser = serial.Serial('/dev/ttyUSB0', 19200, timeout=2)
 
 def sread(address, length, quiet = False):
 	if not quiet: