sw: Add bootrom

LICENSE-MPL-2.0.txt

@@ -0,0 +1,373 @@
+Mozilla Public License Version 2.0
+==================================
+
+1. Definitions
+--------------
+
+1.1. "Contributor"
+    means each individual or legal entity that creates, contributes to
+    the creation of, or owns Covered Software.
+
+1.2. "Contributor Version"
+    means the combination of the Contributions of others (if any) used
+    by a Contributor and that particular Contributor's Contribution.
+
+1.3. "Contribution"
+    means Covered Software of a particular Contributor.
+
+1.4. "Covered Software"
+    means Source Code Form to which the initial Contributor has attached
+    the notice in Exhibit A, the Executable Form of such Source Code
+    Form, and Modifications of such Source Code Form, in each case
+    including portions thereof.
+
+1.5. "Incompatible With Secondary Licenses"
+    means
+
+    (a) that the initial Contributor has attached the notice described
+        in Exhibit B to the Covered Software; or
+
+    (b) that the Covered Software was made available under the terms of
+        version 1.1 or earlier of the License, but not also under the
+        terms of a Secondary License.
+
+1.6. "Executable Form"
+    means any form of the work other than Source Code Form.
+
+1.7. "Larger Work"
+    means a work that combines Covered Software with other material, in 
+    a separate file or files, that is not Covered Software.
+
+1.8. "License"
+    means this document.
+
+1.9. "Licensable"
+    means having the right to grant, to the maximum extent possible,
+    whether at the time of the initial grant or subsequently, any and
+    all of the rights conveyed by this License.
+
+1.10. "Modifications"
+    means any of the following:
+
+    (a) any file in Source Code Form that results from an addition to,
+        deletion from, or modification of the contents of Covered
+        Software; or
+
+    (b) any new file in Source Code Form that contains any Covered
+        Software.
+
+1.11. "Patent Claims" of a Contributor
+    means any patent claim(s), including without limitation, method,
+    process, and apparatus claims, in any patent Licensable by such
+    Contributor that would be infringed, but for the grant of the
+    License, by the making, using, selling, offering for sale, having
+    made, import, or transfer of either its Contributions or its
+    Contributor Version.
+
+1.12. "Secondary License"
+    means either the GNU General Public License, Version 2.0, the GNU
+    Lesser General Public License, Version 2.1, the GNU Affero General
+    Public License, Version 3.0, or any later versions of those
+    licenses.
+
+1.13. "Source Code Form"
+    means the form of the work preferred for making modifications.
+
+1.14. "You" (or "Your")
+    means an individual or a legal entity exercising rights under this
+    License. For legal entities, "You" includes any entity that
+    controls, is controlled by, or is under common control with You. For
+    purposes of this definition, "control" means (a) the power, direct
+    or indirect, to cause the direction or management of such entity,
+    whether by contract or otherwise, or (b) ownership of more than
+    fifty percent (50%) of the outstanding shares or beneficial
+    ownership of such entity.
+
+2. License Grants and Conditions
+--------------------------------
+
+2.1. Grants
+
+Each Contributor hereby grants You a world-wide, royalty-free,
+non-exclusive license:
+
+(a) under intellectual property rights (other than patent or trademark)
+    Licensable by such Contributor to use, reproduce, make available,
+    modify, display, perform, distribute, and otherwise exploit its
+    Contributions, either on an unmodified basis, with Modifications, or
+    as part of a Larger Work; and
+
+(b) under Patent Claims of such Contributor to make, use, sell, offer
+    for sale, have made, import, and otherwise transfer either its
+    Contributions or its Contributor Version.
+
+2.2. Effective Date
+
+The licenses granted in Section 2.1 with respect to any Contribution
+become effective for each Contribution on the date the Contributor first
+distributes such Contribution.
+
+2.3. Limitations on Grant Scope
+
+The licenses granted in this Section 2 are the only rights granted under
+this License. No additional rights or licenses will be implied from the
+distribution or licensing of Covered Software under this License.
+Notwithstanding Section 2.1(b) above, no patent license is granted by a
+Contributor:
+
+(a) for any code that a Contributor has removed from Covered Software;
+    or
+
+(b) for infringements caused by: (i) Your and any other third party's
+    modifications of Covered Software, or (ii) the combination of its
+    Contributions with other software (except as part of its Contributor
+    Version); or
+
+(c) under Patent Claims infringed by Covered Software in the absence of
+    its Contributions.
+
+This License does not grant any rights in the trademarks, service marks,
+or logos of any Contributor (except as may be necessary to comply with
+the notice requirements in Section 3.4).
+
+2.4. Subsequent Licenses
+
+No Contributor makes additional grants as a result of Your choice to
+distribute the Covered Software under a subsequent version of this
+License (see Section 10.2) or under the terms of a Secondary License (if
+permitted under the terms of Section 3.3).
+
+2.5. Representation
+
+Each Contributor represents that the Contributor believes its
+Contributions are its original creation(s) or it has sufficient rights
+to grant the rights to its Contributions conveyed by this License.
+
+2.6. Fair Use
+
+This License is not intended to limit any rights You have under
+applicable copyright doctrines of fair use, fair dealing, or other
+equivalents.
+
+2.7. Conditions
+
+Sections 3.1, 3.2, 3.3, and 3.4 are conditions of the licenses granted
+in Section 2.1.
+
+3. Responsibilities
+-------------------
+
+3.1. Distribution of Source Form
+
+All distribution of Covered Software in Source Code Form, including any
+Modifications that You create or to which You contribute, must be under
+the terms of this License. You must inform recipients that the Source
+Code Form of the Covered Software is governed by the terms of this
+License, and how they can obtain a copy of this License. You may not
+attempt to alter or restrict the recipients' rights in the Source Code
+Form.
+
+3.2. Distribution of Executable Form
+
+If You distribute Covered Software in Executable Form then:
+
+(a) such Covered Software must also be made available in Source Code
+    Form, as described in Section 3.1, and You must inform recipients of
+    the Executable Form how they can obtain a copy of such Source Code
+    Form by reasonable means in a timely manner, at a charge no more
+    than the cost of distribution to the recipient; and
+
+(b) You may distribute such Executable Form under the terms of this
+    License, or sublicense it under different terms, provided that the
+    license for the Executable Form does not attempt to limit or alter
+    the recipients' rights in the Source Code Form under this License.
+
+3.3. Distribution of a Larger Work
+
+You may create and distribute a Larger Work under terms of Your choice,
+provided that You also comply with the requirements of this License for
+the Covered Software. If the Larger Work is a combination of Covered
+Software with a work governed by one or more Secondary Licenses, and the
+Covered Software is not Incompatible With Secondary Licenses, this
+License permits You to additionally distribute such Covered Software
+under the terms of such Secondary License(s), so that the recipient of
+the Larger Work may, at their option, further distribute the Covered
+Software under the terms of either this License or such Secondary
+License(s).
+
+3.4. Notices
+
+You may not remove or alter the substance of any license notices
+(including copyright notices, patent notices, disclaimers of warranty,
+or limitations of liability) contained within the Source Code Form of
+the Covered Software, except that You may alter any license notices to
+the extent required to remedy known factual inaccuracies.
+
+3.5. Application of Additional Terms
+
+You may choose to offer, and to charge a fee for, warranty, support,
+indemnity or liability obligations to one or more recipients of Covered
+Software. However, You may do so only on Your own behalf, and not on
+behalf of any Contributor. You must make it absolutely clear that any
+such warranty, support, indemnity, or liability obligation is offered by
+You alone, and You hereby agree to indemnify every Contributor for any
+liability incurred by such Contributor as a result of warranty, support,
+indemnity or liability terms You offer. You may include additional
+disclaimers of warranty and limitations of liability specific to any
+jurisdiction.
+
+4. Inability to Comply Due to Statute or Regulation
+---------------------------------------------------
+
+If it is impossible for You to comply with any of the terms of this
+License with respect to some or all of the Covered Software due to
+statute, judicial order, or regulation then You must: (a) comply with
+the terms of this License to the maximum extent possible; and (b)
+describe the limitations and the code they affect. Such description must
+be placed in a text file included with all distributions of the Covered
+Software under this License. Except to the extent prohibited by statute
+or regulation, such description must be sufficiently detailed for a
+recipient of ordinary skill to be able to understand it.
+
+5. Termination
+--------------
+
+5.1. The rights granted under this License will terminate automatically
+if You fail to comply with any of its terms. However, if You become
+compliant, then the rights granted under this License from a particular
+Contributor are reinstated (a) provisionally, unless and until such
+Contributor explicitly and finally terminates Your grants, and (b) on an
+ongoing basis, if such Contributor fails to notify You of the
+non-compliance by some reasonable means prior to 60 days after You have
+come back into compliance. Moreover, Your grants from a particular
+Contributor are reinstated on an ongoing basis if such Contributor
+notifies You of the non-compliance by some reasonable means, this is the
+first time You have received notice of non-compliance with this License
+from such Contributor, and You become compliant prior to 30 days after
+Your receipt of the notice.
+
+5.2. If You initiate litigation against any entity by asserting a patent
+infringement claim (excluding declaratory judgment actions,
+counter-claims, and cross-claims) alleging that a Contributor Version
+directly or indirectly infringes any patent, then the rights granted to
+You by any and all Contributors for the Covered Software under Section
+2.1 of this License shall terminate.
+
+5.3. In the event of termination under Sections 5.1 or 5.2 above, all
+end user license agreements (excluding distributors and resellers) which
+have been validly granted by You or Your distributors under this License
+prior to termination shall survive termination.
+
+************************************************************************
+*                                                                      *
+*  6. Disclaimer of Warranty                                           *
+*  -------------------------                                           *
+*                                                                      *
+*  Covered Software is provided under this License on an "as is"       *
+*  basis, without warranty of any kind, either expressed, implied, or  *
+*  statutory, including, without limitation, warranties that the       *
+*  Covered Software is free of defects, merchantable, fit for a        *
+*  particular purpose or non-infringing. The entire risk as to the     *
+*  quality and performance of the Covered Software is with You.        *
+*  Should any Covered Software prove defective in any respect, You     *
+*  (not any Contributor) assume the cost of any necessary servicing,   *
+*  repair, or correction. This disclaimer of warranty constitutes an   *
+*  essential part of this License. No use of any Covered Software is   *
+*  authorized under this License except under this disclaimer.         *
+*                                                                      *
+************************************************************************
+
+************************************************************************
+*                                                                      *
+*  7. Limitation of Liability                                          *
+*  --------------------------                                          *
+*                                                                      *
+*  Under no circumstances and under no legal theory, whether tort      *
+*  (including negligence), contract, or otherwise, shall any           *
+*  Contributor, or anyone who distributes Covered Software as          *
+*  permitted above, be liable to You for any direct, indirect,         *
+*  special, incidental, or consequential damages of any character      *
+*  including, without limitation, damages for lost profits, loss of    *
+*  goodwill, work stoppage, computer failure or malfunction, or any    *
+*  and all other commercial damages or losses, even if such party      *
+*  shall have been informed of the possibility of such damages. This   *
+*  limitation of liability shall not apply to liability for death or   *
+*  personal injury resulting from such party's negligence to the       *
+*  extent applicable law prohibits such limitation. Some               *
+*  jurisdictions do not allow the exclusion or limitation of           *
+*  incidental or consequential damages, so this exclusion and          *
+*  limitation may not apply to You.                                    *
+*                                                                      *
+************************************************************************
+
+8. Litigation
+-------------
+
+Any litigation relating to this License may be brought only in the
+courts of a jurisdiction where the defendant maintains its principal
+place of business and such litigation shall be governed by laws of that
+jurisdiction, without reference to its conflict-of-law provisions.
+Nothing in this Section shall prevent a party's ability to bring
+cross-claims or counter-claims.
+
+9. Miscellaneous
+----------------
+
+This License represents the complete agreement concerning the subject
+matter hereof. If any provision of this License is held to be
+unenforceable, such provision shall be reformed only to the extent
+necessary to make it enforceable. Any law or regulation which provides
+that the language of a contract shall be construed against the drafter
+shall not be used to construe this License against a Contributor.
+
+10. Versions of the License
+---------------------------
+
+10.1. New Versions
+
+Mozilla Foundation is the license steward. Except as provided in Section
+10.3, no one other than the license steward has the right to modify or
+publish new versions of this License. Each version will be given a
+distinguishing version number.
+
+10.2. Effect of New Versions
+
+You may distribute the Covered Software under the terms of the version
+of the License under which You originally received the Covered Software,
+or under the terms of any subsequent version published by the license
+steward.
+
+10.3. Modified Versions
+
+If you create software not governed by this License, and you want to
+create a new license for such software, you may create and use a
+modified version of this License if you rename the license and remove
+any references to the name of the license steward (except to note that
+such modified license differs from this License).
+
+10.4. Distributing Source Code Form that is Incompatible With Secondary
+Licenses
+
+If You choose to distribute Source Code Form that is Incompatible With
+Secondary Licenses under the terms of this version of the License, the
+notice described in Exhibit B of this License must be attached.
+
+Exhibit A - Source Code Form License Notice
+-------------------------------------------
+
+  This Source Code Form is subject to the terms of the Mozilla Public
+  License, v. 2.0. If a copy of the MPL was not distributed with this
+  file, You can obtain one at http://mozilla.org/MPL/2.0/.
+
+If it is not possible or desirable to put the notice in a particular
+file, then You may include the notice in a location (such as a LICENSE
+file in a relevant directory) where a recipient would be likely to look
+for such a notice.
+
+You may add additional accurate notices of copyright ownership.
+
+Exhibit B - "Incompatible With Secondary Licenses" Notice
+---------------------------------------------------------
+
+  This Source Code Form is "Incompatible With Secondary Licenses", as
+  defined by the Mozilla Public License, v. 2.0.

fpga/Makefile

@@ -0,0 +1,68 @@
+# -------------------------------------------------------------------------- --
+#              TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs              --
+# -------------------------------------------------------------------------- --
+# TODO
+# -------------------------------------------------------------------------- --
+# Author       : Markus Koch <markus@notsyncing.net>
+# Contributors : None
+# License      : Mozilla Public License (MPL) Version 2
+# -------------------------------------------------------------------------- --
+
+BUILD_DIR=./build
+VU_DIR=$(BUILD_DIR)/vunit_out
+VU_FLAG=$(VU_DIR)/flag
+
+# Collect VHDL sources using VUnit
+SOURCES_VHDL=$(shell ./run.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')
+
+# Collect Verilog sources using bash
+SERV_DIR=hdl/serv
+SOURCES_VERILOG=$(SERV_DIR)/rtl/*.v
+SOURCES_VERILOG+=$(SERV_DIR)/servant/servant_ram.v $(SERV_DIR)/servant/servant_timer.v
+
+# Miscellaneous sources that when changed must trigger a rebuild
+SOURCES_MISC=../sw/bootrom/bootrom.vhex
+
+# Constraints
+CONSTRAINTS=constraints.pcf
+
+# HW Settings
+YOSYS_DEVICE=u
+DEVICE?=--up5k # --up5k, --u4k
+PACKAGE?=sg48
+
+# Programmer Settings
+PROGRAMMER=ft2232
+
+# ---------------------------------------------------------------------------- #
+
+default: $(BUILD_DIR)/bitstream.bin
+
+$(VU_FLAG): $(SOURCES_VHDL) $(SOURCES_MISC)
+	./run.py --compile -o $(VU_DIR)
+	touch $@
+
+$(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
+	# Collect GHDL sources from VUnit
+	$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
+	yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
+
+$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
+	nextpnr-ice40 $(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
+
+$(BUILD_DIR)/bitstream.bin: $(BUILD_DIR)/netlist-post-pnr.asc
+	icepack $< $@
+
+flash: $(BUILD_DIR)/bitstream.bin
+	openFPGALoader --unprotect-flash -f -c $(PROGRAMMER) -b ice40_generic $<
+
+clean:
+	rm -r $(BUILD_DIR)
+
+.phony: flash clean
+
+# Useful aliases
+compile_vhdl: $(VU_FLAG)
+synth: $(BUILD_DIR)/netlist-post-synthesis.json
+pnr: $(BUILD_DIR)/netlist-post-pnr.asc
+pack: $(BUILD_DIR)/bitstream.bin

fpga/build.sh

@@ -1,28 +0,0 @@
-#!/bin/bash
-
-mkdir -p build
-cd build
-
-set -e
-
-../run.py --compile
-
-BASEDIR=".."
-DEVICE=--u4k # --up5k, --u4k
-PACKAGE=sg48
-
-# Collect pre-analyzed VHDL sources
-GHDLINCDIRS=`find ./vunit_out/ghdl/libraries -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '`
-
-# Collect Verilog sources
-SERV="$BASEDIR/hdl/serv"
-VLOGS=`echo ../hdl/serv/rtl/*.v`
-VLOGS="$VLOGS $SERV/servant/servant_ram.v $SERV/servant/servant_timer.v"
-
-# Synthesize and PnR
-# -device <hx | lp | u>
-yosys -m ghdl -p "read_verilog $VLOGS; ghdl --std=08 $GHDLINCDIRS design.top; synth_ice40 -abc9 -device u -top top -json netlist.json"
-nextpnr-ice40 $DEVICE --package $PACKAGE --freq 12 --asc netlist.asc --report report.json --detailed-timing-report --json netlist.json --pcf ../constraints.pcf 
-
-# Generate bitstream
-icepack netlist.asc bitstream.bin

fpga/constraints.pcf

@@ -23,9 +23,9 @@ set_io pmod[7] 31
 
 set_io uart_rx 37
 set_io uart_tx 36
-set_io clk_12m 35
+set_io clk_50m 35
 
-set_io eth_rx_n 38
+#set_io eth_rx_n 38
 set_io eth_rx_p 42
 
 set_io eth_tx_n[0] 46
@@ -42,3 +42,6 @@ set_io eth_led_green 40
 set_io eth_led_orange 41
 
 set_io led_user 34
+
+set_frequency clk 24
+set_frequency clk_phy 50

fpga/hdl/bench/bench_top_manual.vhd

@@ -73,11 +73,11 @@ begin
 
 	top_inst : entity design.top
 		port map(
-			clk_12m    => clk,
+			clk_50m    => clk,
 			uart_tx    => uart_txd,
 			uart_rx    => uart_rxd,
 			eth_rx_p   => rx_p,
-			eth_rx_n   => rx_n,
+			--eth_rx_n   => rx_n,
 			eth_tx_p   => tx_p,
 			eth_tx_n   => tx_n,
 			psram_ce_n => psram_ce_n,

fpga/hdl/design/pll0.vhd

@@ -11,15 +11,60 @@
 library IEEE;
 use IEEE.std_logic_1164.all;
 
+library generics;
+use generics.ice40_components.all;
+
 entity pll0 is
+	generic(
+		F_CLK     : in integer;
+		F_CLK_PHY : in integer
+	);
 	port(
-		CLKI  : in  std_logic;
+		clk_in      : in  std_logic;
-		CLKOP : out std_logic;
+		clk_out     : out std_logic;
-		LOCK  : out std_logic);
+		clk_out_phy : out std_logic;
+		locked      : out std_logic
+	);
 end pll0;
 
 architecture Structure of pll0 is
+	signal clk_int_osc : std_logic;
 begin
-	CLKOP <= CLKI;
+	SB_HFOSC_inst : component SB_HFOSC
-	LOCK  <= '1';
+		generic map(
+			CLKHF_DIV => "0b01"         -- 24 MHz
+		)
+		port map(
+			CLKHFPU => '1',
+			CLKHFEN => '1',
+			CLKHF   => clk_int_osc
+		);
+
+	--	SB_PLL40_PAD_inst : component SB_PLL40_PAD
+	--		generic map(
+	--			FEEDBACK_PATH => "SIMPLE",
+	--			DIVR          => "0000",
+	--			DIVF          => "1000010",
+	--			DIVQ          => "100",
+	--			FILTER_RANGE  => "001"
+	--		)
+	--		port map(
+	--			RESETB     => '1',
+	--			BYPASS     => '0',
+	--			PACKAGEPIN => clk_in,
+	--			PLLOUTCORE => clk_out_phy
+	--		);
+
+	clk_out_phy <= clk_in;
+
+	-- Not clean, but it works...
+	ckdiv2 : process(clk_out_phy) is
+	begin
+		if rising_edge(clk_out_phy) then
+			clk_out <= not clk_out;
+		end if;
+	end process ckdiv2;
+
+	assert F_CLK = 25000000 report "clk: PLL generates clock different from specified." severity failure;
+	assert F_CLK_PHY = 50000000 report "clk_phy: PLL generates clock different from specified." severity failure;
 end Structure;

fpga/hdl/design/top.vhd

@@ -15,19 +15,17 @@ use ieee.numeric_std.all;
 library generics;
 use generics.all;
 use generics.wishbone_pkg.all;
-
+use generics.ice40_components.all;
-library trashernet;
-use trashernet.all;
 
 entity top is
 	generic(
 		-- System configuration
-		F_CLK     : integer := 12000000;
+		F_CLK     : integer := 25000000;
-		F_CLK_PHY : integer := 48000000;
+		F_CLK_PHY : integer := 50000000;
-		UART_BAUD : integer := 9600
+		UART_BAUD : integer := 19200
 	);
 	port(
-		clk_12m        : in    std_logic; -- System clock
+		clk_50m        : in    std_logic; -- System clock
 
 		-- UART
 		uart_tx        : out   std_logic; -- UART TX
@@ -35,44 +33,41 @@ entity top is
 
 		-- Trashernet
 		eth_rx_p       : in    std_logic; -- Ethernet RX+
-		eth_rx_n       : in    std_logic; -- Ethernet RX-
+		--eth_rx_n       : in    std_logic; -- Ethernet RX-
 		eth_tx_p       : out   std_logic_vector(3 downto 0); -- Ethernet TX+
 		eth_tx_n       : out   std_logic_vector(3 downto 0); -- Ethernet TX-
 
 		-- LEDs
 		eth_led_green  : out   std_logic;
 		eth_led_orange : out   std_logic;
-		led_user       : out   std_logic;
+		led_user       : out   std_logic; --
+
 		-- PSRAM IF
 		psram_ce_n     : out   std_logic;
 		psram_sclk     : out   std_logic;
-		psram_sio      : inout std_logic_vector(3 downto 0);
+		psram_sio      : inout std_logic_vector(3 downto 0); --
+
 		-- Config Flash
 		flash_ce_n     : out   std_logic;
 		flash_sclk     : out   std_logic;
-		flash_sio      : inout std_logic_vector(3 downto 0);
+		flash_sio      : inout std_logic_vector(3 downto 0); --
+
 		-- PMOD
 		pmod           : inout std_logic_vector(7 downto 0)
 	);
 end entity top;
 
 architecture rtl of top is
-	component pll0
-		port(
-			CLKI  : in  std_logic;
-			CLKOP : out std_logic;
-			LOCK  : out std_logic
-		);
-	end component pll0;
-
 	-- System
 	signal pll_locked : std_logic;
 	signal clk        : std_logic;
+	signal clk_phy    : std_logic;
 	signal rst        : std_logic := '1'; -- Asynchronous assert, synchronous release reset
 	signal clr        : std_logic := '1'; -- Fully synchronous reset
 
 	signal eth_tx_p_i : std_logic;
 	signal eth_tx_n_i : std_logic;
+	signal eth_rx_p_i : std_logic;
 
 	-- System Timer
 	signal irq_timer : std_logic;
@@ -120,8 +115,26 @@ architecture rtl of top is
 	                                    or true --
 	                                    -- pragma translate_on
 	                                  ;
-
 begin
+
+	SB_IO_inst : component SB_IO
+		generic map(
+			PIN_TYPE    => "000000",
+			IO_STANDARD => "SB_LVDS_INPUT"
+		)
+		port map(
+			PACKAGE_PIN       => eth_rx_p,
+			LATCH_INPUT_VALUE => '1',
+			CLOCK_ENABLE      => '1',
+			INPUT_CLK         => clk_phy,
+			OUTPUT_CLK        => clk_phy,
+			OUTPUT_ENABLE     => '0',
+			D_OUT_0           => '0',
+			D_OUT_1           => '0',
+			D_IN_0            => eth_rx_p_i,
+			D_IN_1            => open
+		);
+
 	clockgen : if IN_SIMULATION generate
 		clock_driver : process
 			constant period : time := 1 sec / real(F_CLK);
@@ -135,21 +148,31 @@ begin
 		pll_locked <= '1';
 
 	else generate
-		pll_inst : pll0
+		pll_inst : entity work.pll0
+			generic map(
+				F_CLK     => F_CLK,
+				F_CLK_PHY => F_CLK_PHY
+			)
 			port map(
-				CLKI  => clk_12m,
+				clk_in      => clk_50m,
-				CLKOP => clk,
+				clk_out     => clk,
-				LOCK  => pll_locked
+				clk_out_phy => clk_phy,
+				locked      => pll_locked
 			);
 	end generate clockgen;
 
 	por : process(clk) is
-		variable reset_done : std_logic := '0';
+		variable reset_cnt : integer range 0 to 255 := 0;
 	begin
 		if rising_edge(clk) then
-			rst        <= not reset_done;
+			if reset_cnt = 255 then
-			clr        <= not reset_done;
+				rst <= '0';
-			reset_done := '1';
+				clr <= '0';
+			else
+				reset_cnt := reset_cnt + 1;
+				rst       <= '1';
+				clr       <= '1';
+			end if;
 		end if;
 	end process por;
 
@@ -166,7 +189,7 @@ begin
 
 	servant_rom_vhdl_inst : entity work.servant_ram_vhdl
 		generic map(
-			memfile   => "../../sw/bootrom/bootrom.vhex",
+			memfile   => "../sw/bootrom/bootrom.vhex",
 			read_only => true,
 			adr_width => 9
 		)
@@ -200,7 +223,7 @@ begin
 	uart_wb_inst : entity work.uart_wb
 		generic map(
 			F_CLK     => F_CLK,
-			BAUD_RATE => 9600
+			BAUD_RATE => UART_BAUD
 		)
 		port map(
 			clk        => clk,
@@ -218,11 +241,11 @@ begin
 		)
 		port map(
 			clk     => clk,
-			phy_clk => clk,
+			phy_clk => clk_phy,
 			rst     => rst,
 			wb_o    => wb_eth_o,
 			wb_i    => wb_eth_i,
-			rx_p    => eth_rx_p,
+			rx_p    => eth_rx_p_i,
 			tx_p    => eth_tx_p_i,
 			tx_n    => eth_tx_n_i
 		);
@@ -241,7 +264,13 @@ begin
 			mask      => wishbone_masks
 		);
 
-	eth_led_green  <= '0';
+	eth_led_green  <= uart_tx;
-	eth_led_orange <= '1';
+	eth_led_orange <= uart_rx;
-	led_user       <= '1';
+	led_user       <= not psram_ce_n;
+
+	flash_ce_n <= 'Z';
+	flash_sclk <= 'Z';
+	flash_sio  <= (others => 'Z');
+
+	pmod <= (others => 'Z');
 end architecture rtl;

fpga/hdl/design/trashernet_phy_wb.vhd

@@ -16,6 +16,7 @@ library trashernet;
 use trashernet.trashernet_pkg.all;
 
 library generics;
+use generics.all;
 use generics.wishbone_pkg.all;
 
 entity trashernet_phy_wb is
@@ -45,9 +46,15 @@ architecture RTL of trashernet_phy_wb is
 	signal phy_out : phy_out_t;         -- PHY application IF (out)
 	signal phy_in  : phy_in_t;          -- PHY application IF (in)
 
-	signal wb_adr : unsigned(2 downto 0);
+	signal wb_adr : unsigned(2 downto 2);
 
 	signal status_register : std_logic_vector(31 downto 0);
+
+	signal rx_fifo_read  : std_logic;
+	signal rx_fifo_full  : std_logic;
+	signal rx_fifo_empty : std_logic;
+	signal rx_fifo_data  : std_logic_vector(7 downto 0);
+	signal rx_fifo_usage : integer range 0 to 2047;
 begin
 	trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
 		generic map(
@@ -65,22 +72,53 @@ begin
 			tx_n    => tx_n
 		);
 
+	rx_fifo_inst : entity generics.fifo_block
+		generic map(
+			SIZE => 2047
+		)
+		port map(
+			clk        => clk,
+			rst_a      => '0',
+			clr        => rst,
+			data_in    => phy_out.rx_data,
+			write      => phy_out.rx_data_valid,
+			commit     => not phy_out.rx_active,
+			abort      => '0',
+			full       => rx_fifo_full,
+			data_out   => rx_fifo_data,
+			data_first => open,
+			empty      => rx_fifo_empty,
+			read       => rx_fifo_read,
+			usage      => rx_fifo_usage
+		);
+
 	wb_adr <= unsigned(wb_i.adr(wb_adr'range));
 	wbif : process(clk, rst) is
+		variable bytes_rxd : unsigned(15 downto 0);
 	begin
 		if rst then
-			wb_o.ack <= '0';
+			wb_o.ack     <= '0';
+			rx_fifo_read <= '0';
+			bytes_rxd    := (others => '0');
 
 		elsif rising_edge(clk) then
-			wb_o.ack <= '0';
+			wb_o.ack     <= '0';
+			rx_fifo_read <= '0';
 
+			if (phy_out.rx_data_valid = '1') then
+				bytes_rxd := bytes_rxd + 1;
+			end if;
 			if (wb_i.cyc and wb_i.stb) then
 				wb_o.ack <= '1';
 				if wb_adr = 0 then
 					wb_o.dat <= status_register;
 				else
-					wb_o.dat             <= (others => '0');
+					wb_o.dat <= (others => '0');
-					wb_o.dat(7 downto 0) <= phy_out.rx_data; -- TODO: data
+
+					if wb_o.ack = '0' then
+						rx_fifo_read <= '1';
+					end if;
+					wb_o.dat(7 downto 0) <= rx_fifo_data;
 				end if;
 			end if;
 		end if;
@@ -93,5 +131,5 @@ begin
 	phy_in.tx_data_en <= '0';
 	phy_in.tx_data    <= (others => '0');
 
-	status_register <= (x"0000000" & "000" & phy_out.carrier_detect);
+	status_register <= (x"0000" & x"000" & "000" & phy_out.carrier_detect);
 end architecture RTL;

fpga/hdl/generics/fifo_block.vhd

@@ -39,7 +39,7 @@ entity fifo_block is
 		read       : in  std_logic;     -- Acknowledge that `data_out` was read. The word is removed and next one shifted from FIFO when `read and not empty`.
 
 		-- FIFO meta
-		usage      : out integer        -- Usage counter
+		usage      : out integer range 0 to SIZE -- Usage counter
 	);
 end fifo_block;
 
@@ -68,6 +68,7 @@ begin
 			read_pointer_last       <= SIZE - 1;
 			write_pointer_committed <= 0;
 			current_is_first        <= '1';
+			usage                   <= 0;
 
 		elsif rising_edge(clk) then
 			succesful_read  := read and not empty;
@@ -109,6 +110,7 @@ begin
 			if clr then
 				read_pointer            <= 0;
 				write_pointer           <= 0;
+				read_pointer_last       <= SIZE - 1;
 				write_pointer_committed <= 0;
 				current_is_first        <= '1';
 				usage                   <= 0;

fpga/hdl/generics/ice40_components.vhd

@@ -0,0 +1,88 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+package ice40_components is
+	component SB_PLL40_PAD
+		generic(
+			FEEDBACK_PATH : string;
+			DIVR          : std_logic_vector(3 downto 0);
+			DIVF          : std_logic_vector(6 downto 0);
+			DIVQ          : std_logic_vector(2 downto 0);
+			FILTER_RANGE  : std_logic_vector(2 downto 0)
+		);
+		port(
+			RESETB     : in  std_logic;
+			BYPASS     : in  std_logic;
+			PACKAGEPIN : in  std_logic;
+			PLLOUTCORE : out std_logic
+		);
+	end component SB_PLL40_PAD;
+
+	component SB_PLL40_CORE
+		generic(
+			FEEDBACK_PATH : string := "SIMPLE";
+			--			DELAY_ADJUSTMENT_MODE_FEEDBACK : string                       := "FIXED";
+			--			DELAY_ADJUSTMENT_MODE_RELATIVE : string                       := "FIXED";
+			--			PLLOUT_SELECT                  : string                       := "GENCLK";
+			--			SHIFTREG_DIV_MODE              : std_logic;
+			--			FDA_FEEDBACK                   : std_logic_vector(3 downto 0) := "1111";
+			--			FDA_RELATIVE                   : std_logic_vector(3 downto 0) := "1111";
+			DIVR          : std_logic_vector(3 downto 0);
+			DIVF          : std_logic_vector(6 downto 0);
+			DIVQ          : std_logic_vector(2 downto 0);
+			FILTER_RANGE  : std_logic_vector(2 downto 0)
+			--			ENABLE_ICEGATE                 : std_logic                    := '0';
+			--			TEST_MODE                      : std_logic                    := '0'
+		);
+		port(
+			REFERENCECLK : in  std_logic;
+			--			PLLOUTCORE      : out std_logic;
+			PLLOUTGLOBAL : out std_logic;
+			--			EXTFEEDBACK     : in  std_logic;
+			--			DYNAMICDELAY    : in  std_logic_vector(7 downto 0);
+			LOCK         : out std_logic;
+			BYPASS       : in  std_logic;
+			RESETB       : in  std_logic
+			--			LATCHINPUTVALUE : in  std_logic;
+			--			SDO             : out std_logic;
+			--			SDI             : in  std_logic;
+			--			SCLK            : in  std_logic
+		);
+	end component SB_PLL40_CORE;
+
+	component SB_HFOSC
+		generic(
+			CLKHF_DIV : string
+		);
+		port(
+			CLKHFPU : in  std_logic;
+			CLKHFEN : in  std_logic;
+			CLKHF   : out std_logic
+		);
+	end component SB_HFOSC;
+
+	COMPONENT SB_IO IS
+		GENERIC(
+			PIN_TYPE    : std_logic_vector(5 downto 0) := "000000";
+			IO_STANDARD : string                       := "SB_LVDS_INPUT"
+		);
+		PORT(
+			PACKAGE_PIN       : in  std_logic;
+			LATCH_INPUT_VALUE : in  std_logic;
+			CLOCK_ENABLE      : in  std_logic;
+			INPUT_CLK         : in  std_logic;
+			OUTPUT_CLK        : in  std_logic;
+			OUTPUT_ENABLE     : in  std_logic;
+			D_OUT_0           : in  std_logic;
+			D_OUT_1           : in  std_logic;
+			D_IN_0            : out std_logic;
+			D_IN_1            : out std_logic
+		);
+	END COMPONENT SB_IO;
+
+	component SB_GB
+		port(
+			USER_SIGNAL_TO_GLOBAL_BUFFER : in  std_logic;
+			GLOBAL_BUFFER_OUTPUT         : out std_logic);
+	end component;
+end package ice40_components;

fpga/hdl/trashernet

@@ -1 +1 @@
-Subproject commit da7e329939d12e853acbd7636701350babf5e3f4
+Subproject commit 21a0d0e69aeacf9747bfac0262e0d7ca30a691d9

sw/bootrom/.gitignore

@@ -0,0 +1,4 @@
+*.bin
+*.elf
+*.hex
+*.vhex

sw/bootrom/boot.ld

@@ -0,0 +1,45 @@
+__heap_size  = 0x80;
+__stack_size = 0x80;
+
+MEMORY
+{
+	ROM (rwx) : ORIGIN = 0x00000000, LENGTH = 0x100
+	RAM (rwx) : ORIGIN = 0x40000000, LENGTH = 0x400
+}
+SECTIONS
+{
+	.text :
+	{
+		*(.boot)
+		*(.text)
+		*(.text)
+		*(.rodata*)
+	} > ROM
+	.data :
+	{
+		*(.sbss)
+		*(.data)
+		*(.bss)
+		*(.rela*)
+		*(COMMON)
+	} > RAM
+
+	.heap :
+	{
+		. = ALIGN(4);
+		PROVIDE ( end = . );
+		_sheap = .;
+		. = . + __heap_size;
+		. = ALIGN(4);
+		_eheap = .;
+	} >RAM
+
+	.stack :
+	{
+		. = ALIGN(4);
+		_estack = .;
+		. = . + __stack_size;
+		. = ALIGN(4);
+		_sstack = .;
+	} >RAM
+}

sw/bootrom/build.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+set -e
+
+riscv64-elf-gcc -mabi=ilp32 -march=rv32i -nostdlib -nostartfiles -ffreestanding -T boot.ld -Os -o bootrom.elf main.c
+#riscv64-elf-objdump -D bootrom.elf
+riscv64-elf-objcopy -O binary bootrom.elf bootrom.bin
+od --endian=little -vtx4 -An -w4 bootrom.bin | tr -d ' ' > bootrom.vhex
+r2 -A -c 'pdf @ sym._start' -q bootrom.elf

sw/bootrom/main.c

@@ -0,0 +1,87 @@
+#include <inttypes.h>
+
+#define UART0_BASE 0x81000000
+#define UART0_SR (*((volatile uint32_t *) (UART0_BASE + 0x00)))
+#define UART0_DR (*((volatile uint32_t *) (UART0_BASE + 0x04)))
+
+#define UART0_SR_RX_DATA_EMPTY (1 << 0)
+#define UART0_SR_TX_FULL (1 << 1)
+
+/*
+// Set up stack pointer
+asm("_start:\
+	xor sp, sp, sp;\
+	lui sp, 0x80100;\
+	j main;\
+");
+*/
+
+__attribute__((noreturn)) void _start() {
+	uint8_t state = 0;
+	uint8_t c;
+	uint8_t opcode;
+	uint8_t *ptr;
+	uint32_t length;
+
+	/*while (1) {
+		while (UART0_SR & UART0_SR_RX_DATA_EMPTY);
+		c = UART0_DR;
+		while (UART0_SR & UART0_SR_TX_FULL);
+		UART0_DR = c;
+	}*/
+
+	while (1) {
+		while (UART0_SR & UART0_SR_RX_DATA_EMPTY);
+		c = UART0_DR;
+		state++;
+		switch (state) {
+			case 1: // Opcode
+				opcode = c;
+				ptr = 0;
+				length = 0;
+				if (c == 0) // NOP
+					state = 0;
+				break;
+			case 2: // Address
+			case 3:
+			case 4:
+			case 5:
+				ptr = (uint8_t*)(((uint32_t)ptr << 8) | c);
+				if (state != 5)
+					break;
+				if (opcode == 3) { // Jump
+					//((void (*)()) ptr)();
+					asm("jalr %0" : : "r"(ptr)); // Not sure why, but the jump above causes GCC to save variables to the stack at the beginning of this function
+					__builtin_unreachable();
+				}
+				break;
+			case 6: // Length
+			case 7:
+			case 8:
+			case 9:
+				length = (length << 8) | c;
+				if (state != 9)
+					break;
+				if (opcode == 2) { // Read
+					for (; length > 0; length--) {
+						while (UART0_SR & UART0_SR_TX_FULL);
+						UART0_DR = *(ptr);
+						ptr++;
+					}
+					state = 0;
+				}
+				break;
+			case 10: // Write byte by byte
+				*(ptr++) = c;
+				if (--length == 0) {
+					state = 0;
+				} else {
+					state--; // Stay in this state
+				}
+				break;
+			default:
+				break;
+		}
+	}
+	__builtin_unreachable();
+}