trashernet-soc/fpga
2024-09-27 14:42:15 +02:00
..
hdl fpga: bench: Fix top level clock pin name 2024-09-27 14:42:15 +02:00
.gitignore fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
constraints.pcf fpga: Clean up clocking code 2024-08-09 14:01:16 +02:00
Makefile fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
run_physical.py fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
run.py fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00