124 lines
3.1 KiB
VHDL
124 lines
3.1 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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-- ADDR0: RD: [...] TX_BUSY TX_DATA_FULL RX_DATA_EMPTY
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.all;
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use generics.wishbone_pkg.all;
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entity uart_wb is
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generic(
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F_CLK : integer;
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BAUD_RATE : integer := 115200
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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-- Wishbone IF
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wb_o : out wishbone_slave_out; -- Wishbone bus (out)
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wb_i : in wishbone_slave_in; -- Wishbone bus (in)
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serial_out : out std_logic;
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serial_in : in std_logic
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);
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end entity uart_wb;
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architecture rtl of uart_wb is
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signal wb_adr : unsigned(2 downto 0);
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signal status_register : std_logic_vector(31 downto 0);
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signal in_data : std_logic_vector(7 downto 0);
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signal in_data_valid : std_logic;
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signal in_data_available : std_logic;
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signal out_data : std_logic_vector(in_data'range);
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signal out_data_valid : std_logic;
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signal out_data_latched : std_logic;
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signal out_busy : std_logic;
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begin
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uart_tx_inst : entity generics.uart_tx
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generic map(
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F_CLK => F_CLK,
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BAUD_RATE => BAUD_RATE
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)
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port map(
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clk => clk,
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rst_a => rst,
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data => out_data,
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data_valid => out_data_valid,
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data_latched => out_data_latched,
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busy => out_busy,
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serial_out => serial_out
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);
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uart_rx_inst : entity generics.uart_rx
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generic map(
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F_CLK => F_CLK,
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BAUD_RATE => BAUD_RATE
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)
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port map(
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clk => clk,
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rst_a => rst,
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data => in_data,
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data_valid => in_data_valid,
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serial_in_a => serial_in
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);
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wb_adr <= unsigned(wb_i.adr(wb_adr'range));
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status_register <= x"000000" & "00000" & out_busy & out_data_valid & (not in_data_available);
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wb_if : process(clk, rst) is
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begin
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if rst then
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in_data_available <= '0';
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out_data_valid <= '0';
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wb_o.ack <= '0';
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elsif rising_edge(clk) then
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wb_o.ack <= '0';
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if out_data_latched then
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out_data_valid <= '0';
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end if;
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if (wb_i.CYC and wb_i.STB) then
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wb_o.ack <= '1';
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if wb_adr = 0 then -- status reg
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wb_o.dat <= status_register;
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else -- data reg (write to transmit, read to retrieve)
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if wb_i.we then
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out_data <= wb_i.dat(out_data'range);
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out_data_valid <= '1';
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else
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wb_o.dat <= x"000000" & in_data;
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in_data_available <= '0';
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end if;
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end if;
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end if;
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if in_data_valid then
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in_data_available <= '1';
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end if;
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end if;
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end process wb_if;
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wb_o.err <= '0';
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wb_o.stall <= '0';
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wb_o.rty <= '0';
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end architecture rtl;
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