257 lines
7.1 KiB
VHDL
257 lines
7.1 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity aps6404l_controller is
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port(
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clk : in std_logic; -- Max clock 132 MHz -> 66 MHz SPI
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rst : in std_logic; --
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addr : in std_logic_vector(23 downto 0);
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data_in : in std_logic_vector(7 downto 0);
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data_in_next : out std_logic; -- Apply next data word at `data`
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data_out : out std_logic_vector(7 downto 0);
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data_out_valid : out std_logic;
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write_en : in std_logic;
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read_en : in std_logic; --
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psram_ce_n : out std_logic;
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psram_sclk : out std_logic; -- Max clock 66 MHz because of RW mode; Else max clock 90 MHz, else we might violate t_ACLK
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psram_sio : inout std_logic_vector(3 downto 0) --
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);
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end entity aps6404l_controller;
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architecture rtl of aps6404l_controller is
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signal if_latch : std_logic;
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signal if_write : std_logic;
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signal if_output : std_logic; -- Actively drive sio
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type opmode_t is (COMMAND, READ, WRITE);
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signal opmode : opmode_t;
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constant SR_SIZE : integer := 16;
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type sr_element_vector is array (natural range <>) of std_logic_vector(psram_sio'range);
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subtype sr_t is sr_element_vector(0 to SR_SIZE - 1);
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subtype sr_cnt_t is integer range -SR_SIZE to SR_SIZE - 1;
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signal sr : sr_t;
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signal sr_preload : sr_t;
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signal sr_preload_cnt : sr_cnt_t;
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signal sr_load : std_logic;
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signal sr_cnt : sr_cnt_t;
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signal active : std_logic;
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signal rd_second_nibble : std_logic;
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constant RD_WAIT_CNT_MAX : integer := 3 - 1;
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signal rd_wait_cnt : integer range 0 to RD_WAIT_CNT_MAX;
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type state_t is (QPI_EXIT, SPI_RESET1, SPI_RESET2, SPI_ENABLE_QPI, QPI_SET_BOUNDARY, IDLE, READ, WRITE);
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signal state : state_t;
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signal requested : std_logic;
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begin
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clkgen : process(clk, rst) is
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begin
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if rst then
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psram_sclk <= '0';
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if_latch <= '0';
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if_write <= '0';
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elsif rising_edge(clk) then
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if_latch <= '0';
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if_write <= '0';
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if (active) then
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psram_sclk <= not psram_sclk;
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if psram_sclk then -- rising edge
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if_latch <= '1'; -- is the latch edge for both
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else -- falling edge
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if_write <= '1'; -- is a write edge for both
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end if;
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else
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psram_sclk <= '0';
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end if;
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end if;
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end process clkgen;
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sr_p : process(clk, rst) is
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begin
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if rst then
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sr_cnt <= -1;
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psram_ce_n <= '1';
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if_output <= '0';
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active <= '0';
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rd_second_nibble <= '0';
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data_out_valid <= '0';
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data_in_next <= '0';
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rd_wait_cnt <= RD_WAIT_CNT_MAX;
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elsif rising_edge(clk) then
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data_out_valid <= '0';
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data_in_next <= '0';
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if active then
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if if_write then
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sr <= sr(sr'low + 1 to sr'high) & x"-";
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end if;
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if sr_cnt = 0 then
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if if_latch then
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rd_second_nibble <= not rd_second_nibble;
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data_out <= data_out(3 downto 0) & psram_sio;
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end if;
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case opmode is
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when COMMAND =>
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if if_write then -- Transaction end only allowed on write edge
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active <= '0';
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if_output <= '0';
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psram_ce_n <= '1';
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end if;
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when READ =>
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if_output <= '0'; -- Configure as input
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if if_latch and rd_second_nibble then
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if rd_wait_cnt = 0 then
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data_out_valid <= '1';
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else
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rd_wait_cnt <= rd_wait_cnt - 1;
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end if;
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end if;
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when WRITE =>
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if if_write and not rd_second_nibble then
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sr(sr'low to sr'low + 1) <= (data_in(7 downto 4), data_in(3 downto 0));
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data_in_next <= '1';
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end if;
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end case;
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else
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if if_latch then
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sr_cnt <= sr_cnt - 1;
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end if;
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end if;
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else
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rd_wait_cnt <= RD_WAIT_CNT_MAX;
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rd_second_nibble <= '0';
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if_output <= '0';
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if sr_load then
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sr <= sr_preload;
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sr_cnt <= sr_preload_cnt;
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psram_ce_n <= '0';
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if_output <= '1';
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active <= '1';
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end if;
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end if;
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end if;
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end process sr_p;
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psram_sio <= sr(sr'low) when if_output else (others => 'Z');
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fsm : process(clk, rst) is
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function qpi_to_spi(constant DATA : in sr_element_vector) return sr_element_vector is
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variable vec : sr_element_vector(0 to DATA'length * 4 - 1);
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begin
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vec := (others => (others => '-'));
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for i in DATA'range loop
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for j in 0 to 3 loop
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vec(i * 4 + j)(0) := DATA(i)(3 - j);
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end loop;
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end loop;
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return vec;
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end function;
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function addr_to_nibbles(constant ADDR : in std_logic_vector) return sr_element_vector is
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variable vec : sr_element_vector(0 to ADDR'length / 4 - 1);
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begin
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for i in vec'range loop
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vec(i) := ADDR(ADDR'length - (i * 4) - 1 downto ADDR'length - (i + 1) * 4);
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end loop;
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return vec;
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end function addr_to_nibbles;
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impure function qpi_xfer(NIBBLES : sr_element_vector; constant OPM : in opmode_t := COMMAND) return boolean is
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begin
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if (requested) then
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if not active and not sr_load then
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requested <= '0';
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return true;
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end if;
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else
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if not active then
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sr_preload <= (others => x"-");
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sr_preload(NIBBLES'range) <= NIBBLES;
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sr_preload_cnt <= NIBBLES'length - 1;
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sr_load <= '1';
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opmode <= OPM;
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requested <= '1';
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end if;
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end if;
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return false;
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end function qpi_xfer;
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procedure qpi_stop is
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begin
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opmode <= COMMAND;
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end procedure qpi_stop;
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begin
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if rst then
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state <= QPI_EXIT;
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sr_load <= '0';
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requested <= '0';
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opmode <= COMMAND;
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elsif rising_edge(clk) then
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sr_load <= '0';
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case state is
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when QPI_EXIT =>
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state <= SPI_RESET1 when qpi_xfer((x"F", x"5"));
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when SPI_RESET1 =>
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state <= SPI_RESET2 when qpi_xfer(qpi_to_spi((x"6", x"6")));
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when SPI_RESET2 =>
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state <= SPI_ENABLE_QPI when qpi_xfer(qpi_to_spi((x"9", x"9")));
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when SPI_ENABLE_QPI =>
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state <= QPI_SET_BOUNDARY when qpi_xfer(qpi_to_spi((x"3", x"5")));
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when QPI_SET_BOUNDARY =>
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state <= IDLE when qpi_xfer((x"C", x"0"));
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when IDLE =>
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if read_en then
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state <= READ;
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elsif write_en then
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state <= WRITE;
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end if;
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when READ =>
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state <= IDLE when qpi_xfer(sr_element_vector'(x"0", x"B") & addr_to_nibbles(addr), READ);
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if not read_en then
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qpi_stop;
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end if;
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when WRITE =>
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state <= IDLE when qpi_xfer(sr_element_vector'(x"0", x"2") & addr_to_nibbles(addr), WRITE);
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if not write_en then
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qpi_stop;
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end if;
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end case;
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end if;
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end process fsm;
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end architecture rtl;
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