277 lines
7.1 KiB
VHDL
277 lines
7.1 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.all;
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use generics.wishbone_pkg.all;
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use generics.ice40_components.all;
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entity top is
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generic(
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-- System configuration
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F_CLK : integer := 25000000;
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F_CLK_PHY : integer := 50000000;
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UART_BAUD : integer := 19200
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);
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port(
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clk_50m : in std_logic; -- System clock
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-- UART
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uart_tx : out std_logic; -- UART TX
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uart_rx : in std_logic; -- UART RX
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-- Trashernet
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eth_rx_p : in std_logic; -- Ethernet RX+
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--eth_rx_n : in std_logic; -- Ethernet RX-
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eth_tx_p : out std_logic_vector(3 downto 0); -- Ethernet TX+
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eth_tx_n : out std_logic_vector(3 downto 0); -- Ethernet TX-
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-- LEDs
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eth_led_green : out std_logic;
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eth_led_orange : out std_logic;
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led_user : out std_logic; --
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-- PSRAM IF
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psram_ce_n : out std_logic;
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psram_sclk : out std_logic;
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psram_sio : inout std_logic_vector(3 downto 0); --
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-- Config Flash
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flash_ce_n : out std_logic;
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flash_sclk : out std_logic;
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flash_sio : inout std_logic_vector(3 downto 0); --
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-- PMOD
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pmod : inout std_logic_vector(7 downto 0)
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);
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end entity top;
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architecture rtl of top is
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-- System
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signal pll_locked : std_logic;
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signal clk : std_logic;
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signal clk_phy : std_logic;
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signal rst : std_logic := '1'; -- Asynchronous assert, synchronous release reset
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signal clr : std_logic := '1'; -- Fully synchronous reset
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signal eth_tx_p_i : std_logic;
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signal eth_tx_n_i : std_logic;
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signal eth_rx_p_i : std_logic;
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-- System Timer
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signal irq_timer : std_logic;
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-- Wishbone interconnect (master)
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signal wb_masters_o : wishbone_slave_in_vector(1 downto 0);
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signal wb_masters_i : wishbone_slave_out_vector(wb_masters_o'range);
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alias wbi_o is wb_masters_o(0);
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alias wbi_i is wb_masters_i(0);
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alias wbd_o is wb_masters_o(1);
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alias wbd_i is wb_masters_i(1);
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-- Wishbone interconnect (slave)
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signal wb_slaves_o : wishbone_master_in_vector(4 downto 0);
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signal wb_slaves_i : wishbone_master_out_vector(wb_slaves_o'range);
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alias wb_rom_o is wb_slaves_o(0);
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alias wb_rom_i is wb_slaves_i(0);
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alias wb_ram_o is wb_slaves_o(1);
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alias wb_ram_i is wb_slaves_i(1);
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alias wb_timer_o is wb_slaves_o(2);
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alias wb_timer_i is wb_slaves_i(2);
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alias wb_uart_o is wb_slaves_o(3);
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alias wb_uart_i is wb_slaves_i(3);
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alias wb_eth_o is wb_slaves_o(4);
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alias wb_eth_i is wb_slaves_i(4);
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-- Slave address map
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constant wishbone_addresses : wishbone_address_vector := (
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0 => x"00000000", -- Boot ROM
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1 => x"40000000", -- RAM
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2 => x"80000000", -- Timer
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3 => x"81000000", -- UART
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4 => x"82000000" -- Eth
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);
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constant wishbone_masks : wishbone_address_vector := (
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0 => x"FF000000", -- Boot ROM: 256b
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1 => x"FF000000", -- RAM: Max 16M
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2 => x"FF000000", -- Timer
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3 => x"FF000000", -- UART
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4 => x"FF000000" -- Eth
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);
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constant IN_SIMULATION : boolean := false --
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-- pragma translate_off
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or true --
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-- pragma translate_on
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;
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begin
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SB_IO_inst : component SB_IO
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generic map(
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PIN_TYPE => "000000",
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IO_STANDARD => "SB_LVDS_INPUT"
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)
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port map(
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PACKAGE_PIN => eth_rx_p,
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LATCH_INPUT_VALUE => '1',
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CLOCK_ENABLE => '1',
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INPUT_CLK => clk_phy,
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OUTPUT_CLK => clk_phy,
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OUTPUT_ENABLE => '0',
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D_OUT_0 => '0',
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D_OUT_1 => '0',
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D_IN_0 => eth_rx_p_i,
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D_IN_1 => open
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);
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clockgen : if IN_SIMULATION generate
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clock_driver : process
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constant period : time := 1 sec / real(F_CLK);
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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pll_locked <= '1';
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else generate
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pll_inst : entity work.pll0
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk_in => clk_50m,
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clk_out => clk,
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clk_out_phy => clk_phy,
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locked => pll_locked
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);
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end generate clockgen;
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por : process(clk) is
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variable reset_cnt : integer range 0 to 255 := 0;
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begin
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if rising_edge(clk) then
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if reset_cnt = 255 then
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rst <= '0';
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clr <= '0';
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else
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reset_cnt := reset_cnt + 1;
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rst <= '1';
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clr <= '1';
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end if;
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end if;
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end process por;
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serv_top_vhdl_inst : entity work.serv_top_vhdl
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port map(
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clk => clk,
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clr => clr,
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wbi_o => wbi_o,
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wbi_i => wbi_i,
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wbd_o => wbd_o,
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wbd_i => wbd_i,
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irq_timer => irq_timer
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);
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servant_rom_vhdl_inst : entity work.servant_ram_vhdl
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generic map(
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memfile => "../sw/bootrom/bootrom.vhex",
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read_only => true,
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adr_width => 9
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)
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port map(
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clk => clk,
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clr => clr,
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wb_o => wb_rom_o,
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wb_i => wb_rom_i
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);
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aps6404l_wb_inst : entity work.aps6404l_wb
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port map(
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clk => clk,
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rst => rst,
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wb_o => wb_ram_o,
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wb_i => wb_ram_i,
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psram_ce_n => psram_ce_n,
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psram_sclk => psram_sclk,
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psram_sio => psram_sio
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);
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servant_timer_vhdl_inst : entity work.servant_timer_vhdl
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port map(
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clk => clk,
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clr => clr,
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wb_o => wb_timer_o,
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wb_i => wb_timer_i,
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irq => irq_timer
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);
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uart_wb_inst : entity work.uart_wb
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generic map(
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F_CLK => F_CLK,
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BAUD_RATE => UART_BAUD
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)
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port map(
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clk => clk,
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rst => rst,
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wb_o => wb_uart_o,
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wb_i => wb_uart_i,
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serial_out => uart_tx,
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serial_in => uart_rx
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);
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trashernet_phy_wb_inst : entity work.trashernet_phy_wb
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk => clk,
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phy_clk => clk_phy,
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rst => rst,
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wb_o => wb_eth_o,
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wb_i => wb_eth_i,
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rx_p => eth_rx_p_i,
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tx_p => eth_tx_p_i,
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tx_n => eth_tx_n_i
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);
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eth_tx_p <= (others => eth_tx_p_i);
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eth_tx_n <= (others => eth_tx_n_i);
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wishbone_crossbar_inst : entity generics.wishbone_arbiter
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port map(
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clk => clk,
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rst => rst,
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masters_o => wb_masters_o,
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masters_i => wb_masters_i,
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slaves_o => wb_slaves_o,
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slaves_i => wb_slaves_i,
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address => wishbone_addresses,
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mask => wishbone_masks
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);
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eth_led_green <= uart_tx;
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eth_led_orange <= uart_rx;
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led_user <= not psram_ce_n;
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flash_ce_n <= 'Z';
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flash_sclk <= 'Z';
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flash_sio <= (others => 'Z');
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pmod <= (others => 'Z');
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end architecture rtl;
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