This website requires JavaScript.
Explore
Help
Sign In
electronics
/
trashernet-soc
Watch
1
Star
0
Fork
0
You've already forked trashernet-soc
Code
Issues
Pull Requests
Packages
Projects
Releases
Wiki
Activity
4ca35ca18c
trashernet-soc
/
fpga
History
Markus Koch
4ca35ca18c
fpga: aps6404l device model: Print message instead of failing for out of bounds accesses
2024-11-08 10:29:07 +01:00
..
.settings
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
hdl
fpga: aps6404l device model: Print message instead of failing for out of bounds accesses
2024-11-08 10:29:07 +01:00
.gitignore
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
.library_mapping.xml
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
.project
fpga: Add Sigasi / Code project
2024-09-27 14:47:45 +02:00
constraints.pcf
fpga: Clean up clocking code
2024-08-09 14:01:16 +02:00
Makefile
fpga: Cleanly separate build VUnit from bench VUnit
2024-08-01 21:02:32 +02:00
run_physical.py
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00
run.py
fpga: Add NEORV32 as alternative CPU core
2024-09-27 14:44:28 +02:00