98 lines
2.5 KiB
VHDL
98 lines
2.5 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library trashernet;
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use trashernet.trashernet_pkg.all;
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library generics;
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use generics.wishbone_pkg.all;
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entity trashernet_phy_wb is
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generic(
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F_CLK : in integer; -- Clock frequency in Hz
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F_CLK_PHY : in integer
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);
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port(
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-- Global
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clk : in std_logic; -- Global clock
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phy_clk : in std_logic; -- PHY clock
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rst : in std_logic; -- Asynchronous reset
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-- Wishbone IF
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wb_o : out wishbone_slave_out; -- Wishbone bus (out)
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wb_i : in wishbone_slave_in; -- Wishbone bus (in)
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-- Ethernet physical signals
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rx_p : in std_logic;
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tx_p : out std_logic;
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tx_n : out std_logic
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);
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end entity trashernet_phy_wb;
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architecture RTL of trashernet_phy_wb is
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-- PHY application interface
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signal phy_out : phy_out_t; -- PHY application IF (out)
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signal phy_in : phy_in_t; -- PHY application IF (in)
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signal wb_adr : unsigned(2 downto 0);
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signal status_register : std_logic_vector(31 downto 0);
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begin
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trashernet_phy_inst : entity trashernet.trashernet_phy_cdc
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generic map(
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F_CLK => F_CLK,
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F_CLK_PHY => F_CLK_PHY
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)
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port map(
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clk => clk,
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phy_clk => phy_clk,
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rst => rst,
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phy_out => phy_out,
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phy_in => phy_in,
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rx_p => rx_p,
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tx_p => tx_p,
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tx_n => tx_n
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);
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wb_adr <= unsigned(wb_i.adr(wb_adr'range));
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wbif : process(clk, rst) is
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begin
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if rst then
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wb_o.ack <= '0';
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elsif rising_edge(clk) then
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wb_o.ack <= '0';
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if (wb_i.cyc and wb_i.stb) then
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wb_o.ack <= '1';
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if wb_adr = 0 then
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wb_o.dat <= status_register;
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else
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wb_o.dat <= (others => '0');
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wb_o.dat(7 downto 0) <= phy_out.rx_data; -- TODO: data
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end if;
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end if;
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end if;
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end process wbif;
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wb_o.err <= '0';
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wb_o.rty <= '1';
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wb_o.stall <= '0';
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phy_in.tx_data_en <= '0';
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phy_in.tx_data <= (others => '0');
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status_register <= (x"0000000" & "000" & phy_out.carrier_detect);
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end architecture RTL;
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