trashernet-soc/fpga
2024-09-27 16:34:55 +02:00
..
.settings fpga: Add Sigasi / Code project 2024-09-27 14:47:45 +02:00
hdl fpga: ram: Use Verilog model for synthesis and VHDL for simulation 2024-09-27 16:34:55 +02:00
.gitignore fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
.library_mapping.xml fpga: Add Sigasi / Code project 2024-09-27 14:47:45 +02:00
.project fpga: Add Sigasi / Code project 2024-09-27 14:47:45 +02:00
constraints.pcf fpga: Clean up clocking code 2024-08-09 14:01:16 +02:00
Makefile fpga: Cleanly separate build VUnit from bench VUnit 2024-08-01 21:02:32 +02:00
run_physical.py fpga: Add NEORV32 as alternative CPU core 2024-09-27 14:44:28 +02:00
run.py fpga: Add NEORV32 as alternative CPU core 2024-09-27 14:44:28 +02:00