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trashernet-soc
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db5a14a2f0
trashernet-soc
/
fpga
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Markus Koch
db5a14a2f0
fpga: Add generic FIFO core
2024-07-26 10:55:32 +02:00
..
hdl
fpga: Add generic FIFO core
2024-07-26 10:55:32 +02:00
.gitignore
fpga: Implement basic SERV SoC
2024-06-22 11:28:15 +02:00
constraints.pcf
fpga: Implement functional Ethernet controller
2024-07-23 19:13:42 +02:00
Makefile
env: Makefile: Add support for icetime
2024-07-23 18:53:17 +02:00
run.py
env: run.py: Remove unnecessary files from compilation for synthesis
2024-07-07 15:58:32 +02:00