118 lines
2.9 KiB
VHDL
118 lines
2.9 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library device_models;
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library design;
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entity bench_aps6404l_controller is
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end entity bench_aps6404l_controller;
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architecture bench of bench_aps6404l_controller is
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signal rst : std_logic;
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signal clk : std_logic;
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signal psram_ce_n : std_logic;
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signal psram_sclk : std_logic;
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signal psram_sio : std_logic_vector(3 downto 0);
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signal addr : std_logic_vector(23 downto 0);
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signal data_in : std_logic_vector(7 downto 0);
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signal data_in_next : std_logic;
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signal write_en : std_logic;
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signal read_en : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_out_valid : std_logic;
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begin
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aps6404l_controller_inst : entity design.aps6404l_controller
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port map(
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clk => clk,
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rst => rst,
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addr => addr,
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data_in => data_in,
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data_in_next => data_in_next,
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data_out => data_out,
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data_out_valid => data_out_valid,
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write_en => write_en,
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read_en => read_en,
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psram_ce_n => psram_ce_n,
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psram_sclk => psram_sclk,
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psram_sio => psram_sio
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);
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aps6404l_inst : entity device_models.aps6404l
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port map(
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ce_n => psram_ce_n,
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sclk => psram_sclk,
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sio => psram_sio
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);
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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test : process is
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begin
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rst <= '1';
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data_in <= (others => '0');
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read_en <= '0';
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write_en <= '0';
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wait for 1 ns;
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rst <= '0';
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wait for 3 us;
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wait until rising_edge(clk);
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addr <= x"ABCDEF";
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read_en <= '1';
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wait for 2 us;
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wait until rising_edge(clk);
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read_en <= '0';
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wait for 1 us;
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wait until rising_edge(clk);
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addr <= x"ABCDEF";
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write_en <= '1';
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for i in 10 to 15 loop
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data_in <= std_logic_vector(to_unsigned(160 + i, 8));
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loop
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wait until rising_edge(clk);
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exit when data_in_next = '1';
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end loop;
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end loop;
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write_en <= '0';
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wait until rising_edge(clk);
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write_en <= '1';
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for i in 10 to 15 loop
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data_in <= std_logic_vector(to_unsigned(160 + i, 8));
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loop
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wait until rising_edge(clk);
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exit when data_in_next = '1';
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end loop;
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end loop;
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write_en <= '0';
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wait;
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end process test;
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end architecture bench;
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