80 lines
2.8 KiB
Makefile
80 lines
2.8 KiB
Makefile
# -------------------------------------------------------------------------- --
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# TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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# -------------------------------------------------------------------------- --
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# TODO
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# -------------------------------------------------------------------------- --
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# Author : Markus Koch <markus@notsyncing.net>
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# Contributors : None
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# License : Mozilla Public License (MPL) Version 2
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# -------------------------------------------------------------------------- --
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BUILD_DIR=./build
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VU_DIR=$(BUILD_DIR)/vunit_out
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VU_FLAG=$(VU_DIR)/flag
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# Collect VHDL sources using VUnit
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SOURCES_VHDL=$(shell VUNIT_SIMULATOR=ghdl ./run_physical.py -o $(VU_DIR) -f 2>/dev/null | sed -n 's/^\w\+, \(.\+\)$$/\1/p')
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# Collect Verilog sources using bash
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SERV_DIR=hdl/serv
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SOURCES_VERILOG=$(SERV_DIR)/rtl/*.v
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SOURCES_VERILOG+=$(SERV_DIR)/servant/servant_ram.v $(SERV_DIR)/servant/servant_timer.v
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# Miscellaneous sources that when changed must trigger a rebuild
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SOURCES_MISC=../sw/bootrom/bootrom.vhex
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# Constraints
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CONSTRAINTS=constraints.pcf
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# HW Settings
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YOSYS_DEVICE=u
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DEVICE?=up5k # up5k, u4k
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PACKAGE?=sg48
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# Programmer Settings
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PROGRAMMER=ft2232
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# ---------------------------------------------------------------------------- #
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default: $(BUILD_DIR)/bitstream.bin
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$(VU_FLAG): $(SOURCES_VHDL) $(SOURCES_MISC)
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VUNIT_SIMULATOR=ghdl ./run_physical.py --compile -o $(VU_DIR)
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touch $@
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$(BUILD_DIR)/netlist-post-synthesis.json: $(VU_FLAG) $(SOURCES_VERILOG)
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# Collect GHDL sources from VUnit
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$(eval GHDLINCDIRS=$(shell find "$(VU_DIR)/ghdl/libraries" -maxdepth 1 -mindepth 1 -type d | sed "s/^/-P/" | tr '\n' ' '))
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yosys -m ghdl -p "read_verilog $(SOURCES_VERILOG); ghdl --std=08 $(GHDLINCDIRS) design.top; synth_ice40 -abc9 -device $(YOSYS_DEVICE) -top top -json $@"
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$(BUILD_DIR)/netlist-post-pnr.asc: $(BUILD_DIR)/netlist-post-synthesis.json $(CONSTRAINTS)
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nextpnr-ice40 --$(DEVICE) --package $(PACKAGE) --asc $(BUILD_DIR)/netlist-post-pnr.asc --report $(BUILD_DIR)/report.json --detailed-timing-report --json $(BUILD_DIR)/netlist-post-synthesis.json --pcf $(CONSTRAINTS)
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$(BUILD_DIR)/timing.rpt: $(BUILD_DIR)/netlist-post-pnr.asc $(CONSTRAINTS)
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icetime -d $(DEVICE) -P $(PACKAGE) -p $(CONSTRAINTS) -mtr $@ $(BUILD_DIR)/netlist-post-pnr.asc
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$(BUILD_DIR)/bitstream.bin: $(BUILD_DIR)/netlist-post-pnr.asc
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icepack $< $@
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flash: $(BUILD_DIR)/bitstream.bin
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openFPGALoader --unprotect-flash -f -c $(PROGRAMMER) -b ice40_generic $<
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clean:
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# Build artifacts
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rm -rf $(BUILD_DIR)
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# Simulation artifacts
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rm -rf vunit_out
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rm -rf wave.fst*
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simulation:
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./run.py
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.phony: flash clean simulation
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# Useful aliases
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compile_vhdl: $(VU_FLAG)
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synth: $(BUILD_DIR)/netlist-post-synthesis.json
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pnr: $(BUILD_DIR)/netlist-post-pnr.asc
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pack: $(BUILD_DIR)/bitstream.bin
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timing: $(BUILD_DIR)/timing.rpt
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