92 lines
2.9 KiB
VHDL
92 lines
2.9 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.wishbone_pkg.all;
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entity serv_top_vhdl is
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port(
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clk : in std_logic; -- CPU and bus clock
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clr : in std_logic; -- Synchronous clear (CPU reset)
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wbi_o : out wishbone_master_out; -- Instruction Wishbone bus (out)
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wbi_i : in wishbone_master_in; -- Instruction Wishbone bus (in)
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wbd_o : out wishbone_master_out; -- Data Wishbone bus (out)
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wbd_i : in wishbone_master_in; -- Data Wishbone bus (in)
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irq_timer : in std_logic -- System timer interrupt
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);
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end entity serv_top_vhdl;
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architecture rtl of serv_top_vhdl is
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component serv_rf_top
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port(
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clk : in std_logic;
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i_rst : in std_logic;
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i_timer_irq : in std_logic;
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o_ibus_adr : out std_logic_vector(31 downto 0);
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o_ibus_cyc : out std_logic;
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i_ibus_rdt : in std_logic_vector(31 downto 0);
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i_ibus_ack : in std_logic;
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o_dbus_adr : out std_logic_vector(31 downto 0);
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o_dbus_dat : out std_logic_vector(31 downto 0);
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o_dbus_sel : out std_logic_vector(3 downto 0);
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o_dbus_we : out std_logic;
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o_dbus_cyc : out std_logic;
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i_dbus_rdt : in std_logic_vector(31 downto 0);
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i_dbus_ack : in std_logic;
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o_ext_rs1 : out std_logic_vector(31 downto 0);
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o_ext_rs2 : out std_logic_vector(31 downto 0);
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o_ext_funct3 : out std_logic_vector(2 downto 0);
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i_ext_rd : in std_logic_vector(31 downto 0);
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i_ext_ready : in std_logic;
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o_mdu_valid : out std_logic
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);
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end component serv_rf_top;
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signal wbd_o_dat_bv : bit_vector(31 downto 0);
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begin
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serv_top : serv_rf_top
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port map(
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clk => clk,
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i_rst => clr,
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i_timer_irq => irq_timer,
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o_ibus_adr => wbi_o.adr,
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o_ibus_cyc => wbi_o.cyc,
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i_ibus_rdt => wbi_i.dat,
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i_ibus_ack => wbi_i.ack,
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o_dbus_adr => wbd_o.adr,
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o_dbus_dat => wbd_o.dat,
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o_dbus_sel => wbd_o.sel,
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o_dbus_we => wbd_o.we,
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o_dbus_cyc => wbd_o.cyc,
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i_dbus_rdt => wbd_i.dat,
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i_dbus_ack => wbd_i.ack,
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o_ext_rs1 => open,
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o_ext_rs2 => open,
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o_ext_funct3 => open,
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i_ext_rd => (others => '0'),
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i_ext_ready => '0',
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o_mdu_valid => open
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);
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--wbd_o.dat <= to_std_logic_vector(wbd_o_dat_bv);
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wbi_o.stb <= wbi_o.cyc;
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wbi_o.sel <= (others => '1');
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wbi_o.we <= '0';
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wbi_o.dat <= (others => '0');
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wbd_o.stb <= wbd_o.cyc;
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end architecture rtl;
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