66 lines
1.7 KiB
VHDL
66 lines
1.7 KiB
VHDL
-- -------------------------------------------------------------------------- --
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-- TRASHERNET SoC - A Trashy Ethernet SoC for FPGAs --
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-- -------------------------------------------------------------------------- --
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-- TODO
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-- -------------------------------------------------------------------------- --
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-- Author : Markus Koch <markus@notsyncing.net>
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-- Contributors : None
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-- License : Mozilla Public License (MPL) Version 2
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library generics;
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use generics.wishbone_pkg.all;
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entity servant_timer_vhdl is
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port(
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clk : in std_logic; -- CPU and bus clock
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clr : in std_logic; -- Synchronous clear (CPU reset)
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wb_o : out wishbone_slave_out; -- Wishbone bus (out)
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wb_i : in wishbone_slave_in; -- Wishbone bus (in)
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irq : out std_logic -- System Timer Interrupt
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);
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end entity servant_timer_vhdl;
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architecture rtl of servant_timer_vhdl is
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component servant_timer
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generic(
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WIDTH : integer
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);
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port(
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i_clk : in std_logic;
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i_rst : in std_logic;
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o_irq : out std_logic;
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i_wb_dat : in std_logic_vector;
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i_wb_we : in std_logic;
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i_wb_cyc : in std_logic;
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o_wb_dat : out std_logic_vector
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);
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end component servant_timer;
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begin
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servant_timer_inst : component servant_timer
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generic map(
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WIDTH => 32
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)
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port map(
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i_clk => clk,
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i_rst => clr,
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o_irq => irq,
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i_wb_dat => wb_i.dat,
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i_wb_we => wb_i.we,
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i_wb_cyc => wb_i.cyc and wb_i.stb,
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o_wb_dat => wb_o.dat
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);
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wb_o.ack <= '1';
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wb_o.rty <= '0';
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wb_o.err <= '0';
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wb_o.stall <= '0';
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end architecture rtl;
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