ttl-fpga/sw/kousaten/src/main.c

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#include <stdio.h>
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#include "fpga_cell.h"
#include "fpga_fdef_loader.h"
#include "fpga_global.h"
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#include "fpga.h"
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#include "unistd.h"
#include "string.h"
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#include "fpga_cell_lut34.h" /* For testing purposes only */
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#define E_FDEF 1
#define E_BITSTREAM 2
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int development_test_main(int argc, char *argv[])
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{
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struct fpga_cell *entry_cell;
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struct fpga_chain *chain;
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int opt;
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char *fdef_filename = "fdef/4x4.fdef";
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char *kst_filename = "-";
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char *bitstream_filename = "-";
int bitstream_ascii = 0;
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set_log_level(LL_DEBUG);
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while((opt = getopt(argc, argv, "f:i:o:h")) != -1)
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{
switch(opt)
{
case 'f':
fdef_filename = optarg;
break;
case 'i':
kst_filename = optarg;
report(LL_WARNING, "Input not yet implemented.");
break;
case 'o':
bitstream_filename = optarg;
break;
case 'h':
bitstream_ascii = 1;
break;
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case ':':
case '?':
printf("Usage: %s [-f fdef] [-i input.kst] [-o output.bin] [-h]\n"
"Generate bitstreams for the TTL-FPGA.\n\n"
"When INPUT or OUTPUT is -, read/write standard input.\n\n"
" -f\tFDEF FPGA description file, default fdef/4x4.fdef\n"
" -i\tKousaten input file, default stdin\n"
" -o\tOutput file, default stdout\n"
" -h\tGenerate output as ASCII HEX\n",
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argv[0]);
return 0;
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default:
break;
}
}
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entry_cell = fpga_fdef_loader_load(fdef_filename);
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if (!entry_cell) {
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report(LL_CRITICAL, "Error loading FDEF.");
return E_FDEF;
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}
report(LL_INFO, "FDEF loaded.");
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chain = fpga_isp_chain_new(entry_cell);
if (!chain) {
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report(LL_CRITICAL, "Critical error during bitstream generation.");
return E_BITSTREAM;
}
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report(LL_INFO, "Chain loaded.");
/* TODO: Configure application specific logic */
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[0] = LUT_NET_F0;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[1] = LUT_NET_F2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[2] = LUT_NET_L2;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[3] = LUT_NET_L3;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 1;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'A';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[1] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[2] = 'B';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[3] = 'Z';
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->route_en = (1 << ROUTE_T0) | (1 << ROUTE_T1) | (1 << ROUTE_T2) | (1 << ROUTE_T3);
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[0] = 0b01100110;
((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->LUT3[1] = 0b01010101;
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if (fpga_generate_bitstream(chain, bitstream_filename, bitstream_ascii)) {
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report(LL_ERROR, "Bitstream generation failed.");
return E_BITSTREAM;
}
report(LL_INFO, "Generated bitstream.");
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return 0;
}
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int main(int argc, char *argv[])
{
return development_test_main(argc, argv);
}