parent
9a06c054e8
commit
f60d76f831
@ -19,7 +19,7 @@ static int LUT3_BITMAP[2][8] = {
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};
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/* LUT Config Definitions */
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static int BIT_LUT_SYNC = 20;
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static int BIT_LUT_SYNC_N = 20;
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static int BIT_LUT_SPLIT_N = 21;
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/* LUT IN MUX Definitions */
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@ -178,7 +178,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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fix_bitfields(ROUTE_BITMAP, 8);
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fix_bitfields(&BIT_LED_LUT_IN, 1);
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fix_bitfields(&BIT_LED_LUT_OUT_N, 1);
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fix_bitfields(&BIT_LUT_SYNC, 1);
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fix_bitfields(&BIT_LUT_SYNC_N, 1);
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fix_bitfields(&BIT_LUT_SPLIT_N, 1);
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}
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@ -254,7 +254,7 @@ char *fpga_cell_lut34_isp_generate_bitstream(struct fpga_cell *cell)
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BS_SET_BIT(BIT_LUT_SPLIT_N, 0, "Couldn't set LUT3-2 mode. Did you configure a LUT4 before?");
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}
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}
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BS_SET_BIT(BIT_LUT_SYNC, lut34->sync, "Couldn't %s synchronous mode.",
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BS_SET_BIT(BIT_LUT_SYNC_N, !lut34->sync, "Couldn't %s synchronous mode.",
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(lut34->sync ? "enabling" : "disabling"));
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/* Basic check whether each bit has been configured */
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@ -76,7 +76,7 @@ int development_test_main(int argc, char *argv[])
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[1] = LUT_NET_F2;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[2] = LUT_NET_L2;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->lut_in_sel[3] = LUT_NET_L3;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 0;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->sync = 1;
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[0] = 'A';
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((struct fpga_cell_lut34 *)(entry_cell->cell_connections[RIGHT]))->drive_sel[1] = 'Z';
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