23 lines
358 B
Plaintext
23 lines
358 B
Plaintext
|
EESchema Schematic File Version 4
|
||
|
EELAYER 29 0
|
||
|
EELAYER END
|
||
|
$Descr A4 11693 8268
|
||
|
encoding utf-8
|
||
|
Sheet 1 3
|
||
|
Title "DISCRETE TTL FPGA"
|
||
|
Date ""
|
||
|
Rev "01"
|
||
|
Comp "Markus Koch <markus@notsyncing.net>"
|
||
|
Comment1 "PCB"
|
||
|
Comment2 ""
|
||
|
Comment3 ""
|
||
|
Comment4 ""
|
||
|
$EndDescr
|
||
|
$Sheet
|
||
|
S 4450 2100 3050 1050
|
||
|
U 5D77FDBE
|
||
|
F0 "LogicBlock" 50
|
||
|
F1 "logic_block.sch" 50
|
||
|
$EndSheet
|
||
|
$EndSCHEMATC
|