electronics/ttl-fpga
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Fix right and bottom bus connections

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Fixes #2.
This commit is contained in:
Markus Koch 2019-06-01 18:20:26 +02:00
parent 76b1d2d01f
commit 6b2fa97a6f
1 changed files with 25 additions and 7 deletions
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32
logic_block.sch
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@ -1876,10 +1876,6 @@ Wire Wire Line
14450 7400 14150 7400
Wire Wire Line
14450 6950 13700 6950
Wire Wire Line
14450 6500 13250 6500
Wire Wire Line
14450 6050 12800 6050
Text Label 12250 7100 0 50 ~ 0
cfg7
Text Label 12250 6650 0 50 ~ 0
@ -1906,8 +1902,6 @@ Connection ~ 13700 6950
Wire Wire Line
13700 6950 13700 5600
Connection ~ 14150 7400
Wire Wire Line
14150 7400 14150 5600
Text Label 12850 6050 0 50 ~ 0
fabric0
Text Label 13300 6500 0 50 ~ 0
@ -2105,7 +2099,7 @@ Wire Bus Line
Connection ~ 13500 7850
Text HLabel 13500 7950 3 50 BiDi ~ 0
fabric_b[3..0]
Text Label 14200 7400 0 50 ~ 0
Text Label 14150 7400 0 50 ~ 0
fabric3
Text Notes 7900 4850 0 50 ~ 0
cfg[15..8]
@ -2480,6 +2474,30 @@ Wire Wire Line
9650 8250 9750 8250
Text Notes 5200 7950 0 50 ~ 0
*
Text Label 14150 7750 1 50 Italic 0
fabric_b3
Text Label 13700 7750 1 50 Italic 0
fabric_b2
Text Label 13250 7750 1 50 Italic 0
fabric_b1
Text Label 12800 7750 1 50 Italic 0
fabric_b0
Text Label 14450 6050 0 50 Italic 0
fabric_r0
Wire Wire Line
14150 6050 14150 5600
Wire Wire Line
14150 7400 14150 6050
Wire Wire Line
14450 6500 13250 6500
Wire Wire Line
12800 6050 14450 6050
Text Label 14450 6500 0 50 Italic 0
fabric_r1
Text Label 14450 6950 0 50 Italic 0
fabric_r2
Text Label 14450 7400 0 50 Italic 0
fabric_r3
Wire Bus Line
12900 7850 13500 7850
Wire Bus Line