electronics/ttl-fpga
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Update global project config for PCBWay's rules

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This commit is contained in:
Markus Koch 2019-06-04 21:11:08 +02:00
parent a62036545c
commit 798144c729
1 changed files with 11 additions and 11 deletions
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22
ttl-fpga.pro
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@ -1,4 +1,4 @@
update=Thu 30 May 2019 02:28:07 PM CEST update=Sat 01 Jun 2019 09:25:42 PM CEST
version=1 version=1
last_client=kicad last_client=kicad
[general] [general]
@ -22,15 +22,15 @@ AllowMicroVias=0
AllowBlindVias=0 AllowBlindVias=0
RequireCourtyardDefinitions=0 RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1 ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2 MinTrackWidth=0.1524
MinViaDiameter=0.4 MinViaDiameter=0.4
MinViaDrill=0.3 MinViaDrill=0.3
MinMicroViaDiameter=0.2 MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999 MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25 MinHoleToHole=0.25
TrackWidth1=0.25 TrackWidth1=0.1524
ViaDiameter1=0.8 ViaDiameter1=0.6
ViaDrill1=0.4 ViaDrill1=0.3
dPairWidth1=0.2 dPairWidth1=0.2
dPairGap1=0.25 dPairGap1=0.25
dPairViaGap1=0.25 dPairViaGap1=0.25
@ -57,7 +57,7 @@ OthersTextUpright=1
SolderMaskClearance=0.051 SolderMaskClearance=0.051
SolderMaskMinWidth=0.25 SolderMaskMinWidth=0.25
SolderPasteClearance=0 SolderPasteClearance=0
SolderPasteRatio=0 SolderPasteRatio=-0
[pcbnew/Layer.F.Cu] [pcbnew/Layer.F.Cu]
Name=F.Cu Name=F.Cu
Type=0 Type=0
@ -223,14 +223,14 @@ Enabled=1
[pcbnew/Layer.F.Fab] [pcbnew/Layer.F.Fab]
Enabled=1 Enabled=1
[pcbnew/Layer.Rescue] [pcbnew/Layer.Rescue]
Enabled=1 Enabled=0
[pcbnew/Netclasses] [pcbnew/Netclasses]
[pcbnew/Netclasses/Default] [pcbnew/Netclasses/Default]
Name=Default Name=Default
Clearance=0.2 Clearance=0.1524
TrackWidth=0.25 TrackWidth=0.1524
ViaDiameter=0.8 ViaDiameter=0.6
ViaDrill=0.4 ViaDrill=0.3
uViaDiameter=0.3 uViaDiameter=0.3
uViaDrill=0.1 uViaDrill=0.1
dPairWidth=0.2 dPairWidth=0.2